<div dir="ltr">On 24 May 2013 13:56, Eric Anholt <<a href="mailto:eric@anholt.net" target="_blank">eric@anholt.net</a>> wrote: <div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> For a blit-uploaded temporary, it's faster on current hardware to memcpy the data into a linear CPU mapping than to go through the GTT. --- src/mesa/drivers/dri/intel/intel_fbo.c | 2 +- src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 22 +++++++++++++--------- src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 2 +- src/mesa/drivers/dri/intel/intel_tex_image.c | 2 +- src/mesa/drivers/dri/intel/intel_tex_validate.c | 2 +- 5 files changed, 17 insertions(+), 13 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 05ff784..73ed91d 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -924,7 +924,7 @@ intel_renderbuffer_move_to_temp(struct intel_context *intel, width, height, depth, true, irb->mt->num_samples, - false /* force_y_tiling */); + 0 /* force_tiling_mask */); if (intel->vtbl.is_hiz_depth_format(intel, new_mt->format)) { intel_miptree_alloc_hiz(intel, new_mt); diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index c3e55f4..d41fbdf 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -265,7 +265,7 @@ intel_miptree_create_layout(struct intel_context *intel, mt->logical_depth0, true, num_samples, - false /* force_y_tiling */); + 0 /* force_tiling_mask */); if (!mt->stencil_mt) { intel_miptree_release(&mt); return NULL; @@ -309,7 +309,7 @@ intel_miptree_choose_tiling(struct intel_context *intel, gl_format format, uint32_t width0, uint32_t num_samples, - bool force_y_tiling, + int force_tiling_mask, struct intel_mipmap_tree *mt) { @@ -320,8 +320,12 @@ intel_miptree_choose_tiling(struct intel_context *intel, return I915_TILING_NONE; } - if (force_y_tiling) - return I915_TILING_Y; + /* Some usages may want only one type of tiling, like depth miptrees (Y + * tiled), or temporary BOs for uploading data once (linear). So far the + * mask only ever has one bit set. + */ + if (force_tiling_mask) + return ffs(force_tiling_mask) - 1; </blockquote><div> </div><div>I'm not comfortable with the meaning of force_tiling_mask. Effectively at the moment it's: </div><div>- 0 means all tiling formats are allowed </div><div>- (1 << n) means tiling format is required to be n </div><div>- any other value is undefined. </div><div>I'd prefer to see an "allowed_tiling_mask" where we set bit n if and only if tiling mode n is allowed. </div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> if (num_samples > 1) { /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled @@ -375,7 +379,7 @@ intel_miptree_create(struct intel_context *intel, GLuint depth0, bool expect_accelerated_upload, GLuint num_samples, - bool force_y_tiling) + int force_tiling_mask) { struct intel_mipmap_tree *mt; gl_format tex_format = format; @@ -441,7 +445,7 @@ intel_miptree_create(struct intel_context *intel, } uint32_t tiling = intel_miptree_choose_tiling(intel, format, width0, - num_samples, force_y_tiling, + num_samples, force_tiling_mask, mt); bool y_or_x = tiling == (I915_TILING_Y | I915_TILING_X); @@ -570,7 +574,7 @@ intel_miptree_create_for_renderbuffer(struct intel_context *intel, mt = intel_miptree_create(intel, GL_TEXTURE_2D, format, 0, 0, width, height, depth, true, num_samples, - false /* force_y_tiling */); + 0 /* force_tiling_mask */); if (!mt) goto fail; @@ -1008,7 +1012,7 @@ intel_miptree_alloc_mcs(struct intel_context *intel, mt->logical_depth0, true, 0 /* num_samples */, - true /* force_y_tiling */); + (1 << I915_TILING_Y)); /* From the Ivy Bridge PRM, Vol 2 Part 1 p326: * @@ -1089,7 +1093,7 @@ intel_miptree_alloc_hiz(struct intel_context *intel, mt->logical_depth0, true, mt->num_samples, - false /* force_y_tiling */); + 0 /* force_tiling_mask */); if (!mt->hiz_mt) return false; diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h index 543182a..4ccbd0d 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h @@ -399,7 +399,7 @@ struct intel_mipmap_tree *intel_miptree_create(struct intel_context *intel, GLuint depth0, bool expect_accelerated_upload, GLuint num_samples, - bool force_y_tiling); + int force_tiling_mask); struct intel_mipmap_tree * intel_miptree_create_layout(struct intel_context *intel, diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c index 4e307f8..a3928bb 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_image.c +++ b/src/mesa/drivers/dri/intel/intel_tex_image.c @@ -103,7 +103,7 @@ intel_miptree_create_for_teximage(struct intel_context *intel, depth, expect_accelerated_upload, intelImage->base.Base.NumSamples, - false /* force_y_tiling */); + 0 /* force_tiling_mask */); } /* XXX: Do this for TexSubImage also: diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c b/src/mesa/drivers/dri/intel/intel_tex_validate.c index eaa2561..8f43db5 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_validate.c +++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c @@ -106,7 +106,7 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit) depth, true, 0 /* num_samples */, - false /* force_y_tiling */); + 0 /* force_tiling_mask */); if (!intelObj->mt) return false; } -- 1.8.3.rc0 _______________________________________________ mesa-dev mailing list <a href="mailto:mesa-dev@lists.freedesktop.org">mesa-dev@lists.freedesktop.org</a> <a href="http://lists.freedesktop.org/mailman/listinfo/mesa-dev" target="_blank">http://lists.freedesktop.org/mailman/listinfo/mesa-dev</a> </blockquote></div> </div></div>