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<body class='hmmessage'><div dir='ltr'><div style="color: rgb(34, 34, 34); font-family: arial, sans-serif; font-size: 13px;">Hi there,</div><div style="color: rgb(34, 34, 34); font-family: arial, sans-serif; font-size: 13px;"><br></div><div style="color: rgb(34, 34, 34); font-family: arial, sans-serif; font-size: 13px;">I am a new user of OpenGL and Nios ii soft processor. Currently, I am working on a project related to OpenGL and Nios ii.</div><div style="color: rgb(34, 34, 34); font-family: arial, sans-serif; font-size: 13px;"><br></div><span style="color: rgb(34, 34, 34); font-family: arial, sans-serif; font-size: 13px;">For this project, I will implement Nios ii soft core processor on Altera DE2 ( an FPGA board). Then I will compile some OpenGL applications with Nios ii IDE for Eclipse and download it onto the embedded system board. The problem is that there is no OpenGL library for this system so I have to modify mesa library to achieve this goal.</span><div style="color: rgb(34, 34, 34); font-family: arial, sans-serif; font-size: 13px;"><br></div><div style="color: rgb(34, 34, 34); font-family: arial, sans-serif; font-size: 13px;">Specifically, this Nios ii processor is a general-purpose RISC processor with following features:</div><div style="color: rgb(34, 34, 34); font-family: arial, sans-serif; font-size: 13px;"><br></div><div style="color: rgb(34, 34, 34); font-family: arial, sans-serif; font-size: 13px;"><div><font color="#333333" face="Verdana, Arial, Helvetica, sans-serif"><span style="font-size: 11px; line-height: 14.84375px;"><i> Full 32-bit instruction set, data path, and address space</i></span></font></div><div><font color="#333333" face="Verdana, Arial, Helvetica, sans-serif"><span style="font-size: 11px; line-height: 14.84375px;"><i>¡á 32 general-purpose registers</i></span></font></div><div><font color="#333333" face="Verdana, Arial, Helvetica, sans-serif"><span style="font-size: 11px; line-height: 14.84375px;"><i>¡á Optional shadow register sets</i></span></font></div><div><font color="#333333" face="Verdana, Arial, Helvetica, sans-serif"><span style="font-size: 11px; line-height: 14.84375px;"><i>¡á 32 interrupt sources</i></span></font></div><div><font color="#333333" face="Verdana, Arial, Helvetica, sans-serif"><span style="font-size: 11px; line-height: 14.84375px;"><i>¡á External interrupt controller interface for more interrupt sources</i></span></font></div><div><font color="#333333" face="Verdana, Arial, Helvetica, sans-serif"><span style="font-size: 11px; line-height: 14.84375px;"><i>¡á Single-instruction 32 ¡¿ 32 multiply and divide producing a 32-bit result</i></span></font></div><div><font color="#333333" face="Verdana, Arial, Helvetica, sans-serif"><span style="font-size: 11px; line-height: 14.84375px;"><i>¡á Dedicated instructions for computing 64-bit and 128-bit products of multiplication</i></span></font></div><div><font color="#333333" face="Verdana, Arial, Helvetica, sans-serif"><span style="font-size: 11px; line-height: 14.84375px;"><div style="font-style: italic;">¡á Floating-point instructions for single-precision floating-point operations</div><div style="font-style: italic;">¡á Single-instruction barrel shifter</div><div style="font-style: italic;">¡á Access to a variety of on-chip peripherals, and interfaces to off-chip memories and </div><div style="font-style: italic;">peripherals</div><div style="font-style: italic;">¡á Hardware-assisted debug module enabling processor start, stop, step, and trace </div><div style="font-style: italic;">under control of the Nios II software development tools</div><div style="font-style: italic;">¡á Optional memory management unit (MMU) to support operating systems that </div><div style="font-style: italic;">require MMUs</div><div style="font-style: italic;">¡á Optional memory protection unit (MPU)</div><div style="font-style: italic;">¡á Software development environment based on the GNU C/C++ tool chain and the </div><div style="font-style: italic;">Nios II Software Build Tools (SBT) for Eclipse</div><div style="font-style: italic;">¡á Integration with Altera's SignalTap¢ç II Embedded Logic Analyzer, enabling </div><div style="font-style: italic;">real-time analysis of instructions and data along with other signals in the FPGA </div><div style="font-style: italic;">design</div><div style="font-style: italic;">¡á Instruction set architecture (ISA) compatible across all Nios II processor systems</div><div style="font-style: italic;">¡á Performance up to 250 DMIPS</div><div style="font-style: italic;"><br></div><div>Can anyone give me some suggestions where to start the project? Thanks</div></span></font></div></div> </div></body>
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