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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [softpipe] glxgears floating point exception"
href="https://bugs.freedesktop.org/show_bug.cgi?id=66806#c2">Comment # 2</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [softpipe] glxgears floating point exception"
href="https://bugs.freedesktop.org/show_bug.cgi?id=66806">bug 66806</a>
from <span class="vcard"><a class="email" href="mailto:jfonseca@vmware.com" title="José Fonseca <jfonseca@vmware.com>"> <span class="fn">José Fonseca</span></a>
</span></b>
<pre>Indeed
<a href="http://software.intel.com/en-us/articles/x87-and-sse-floating-point-assists-in-ia-32-flush-to-zero-ftz-and-denormals-are-zero-daz">http://software.intel.com/en-us/articles/x87-and-sse-floating-point-assists-in-ia-32-flush-to-zero-ftz-and-denormals-are-zero-daz</a>
suggests to mask certain exceptions together with the FTZ/DAZ bits:
// UNDERFLOWS
set_mxcsr_on(FTZ_BIT);
set_mxcsr_off(UNDERFLOW_EXCEPTION_MASK);
make_denormal();
clear_flags();
// DENORMALS
set_mxcsr_off(DAZ_BIT);
set_mxcsr_on(DENORMAL_EXCEPTION_MASK);
make_denormal();
clear_flags();
So we should probably do the same.</pre>
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