<div dir="ltr">On 19 July 2013 17:32, Jordan Justen <span dir="ltr"><<a href="mailto:jordan.l.justen@intel.com" target="_blank">jordan.l.justen@intel.com</a>></span> wrote:<br><div class="gmail_extra"><div class="gmail_quote">
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">git://<a href="http://people.freedesktop.org/~jljusten/mesa" target="_blank">people.freedesktop.org/~jljusten/mesa</a> ivb-full-depth-buffer-v2<br>
<br>
This series converts DEPTH_BUFFER to use the LOD and<br>
minimum array element fields and always points the<br>
depth, hiz and stencil buffers at the top of the<br>
miptree surface.<br>
<br>
This should allows us to support layered rendering,<br>
although testing of this is not completed. Layered<br>
rendering will be required for GL 3.2 / GLSL 1.50<br>
support, but it can also be exposed via the<br>
GL_AMD_vertex_shader_layer extension.<br>
<br>
v2:<br>
* New patch 8<br>
"gen7 fbo: make unmatched depth/stencil configs return unsupported"<br>
* Patch 11 is re-written based on code review<br>
"i965 gen7: don't set FORCE_ZERO_RTAINDEX for layered rendering"<br>
* New patch 12<br>
"intel_mipmap_tree: all layers need hiz resolves with layered rendering"<br>
* Note: all other patches have been reviewed-by Paul<br></blockquote><div><br></div><div>I sent comments on patches 8 and 12. Patch 11 is:<br><br></div><div>Reviewed-by: Paul Berry <<a href="mailto:stereotype441@gmail.com" target="_blank">stereotype441@gmail.com</a>><br>
<br>There are two other things that I think need to happen which haven't been addressed yet:<br><br></div><div>- The HiZ allocation code needs to be changed to follow the formulas in Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Depth and Stencil > Hierarchical Depth Buffer now, since the hardware is now in charge of the layout of the miptree in the HiZ buffer, and the layout it uses may not be the same as the layout that was assumed by our HiZ allocation functions before.<br>
<br></div><div>- When glClear() is applied to a layered framebuffer, all layers must be cleared. I don't think we've got any code to do that yet. Note that there are a number of different clear paths that may need to be addressed (brw_blorp_clear_color(), brw_fast_clear_depth(), _mesa_meta_Clear(), _mesa_meta_glsl_Clear(), and _swrast_Clear(), I think). The starting point for all these functions is brw_clear().<br>
<br></div><div><br>Finally, there are two other rules about layered rendering that I believe we implement correctly, but it would be nice to have some piglit tests: 1. glReadBuffer() applied to a layered framebuffer always reads from layer 0. 2. glBlitFramebuffer() using a layered framebuffer as a source always reads from layer 0 (even when the destination buffer is also layered).<br>
</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<br>
Testing on IVB and HSW:<br>
* Piglit: Fixes array-depth-roundtrip<br>
<br>
Testing on IVB:<br>
* AMD_vertex_shader_layer piglit tests on list<br>
* Basic visual inspection of Unigine Tropics<br>
* Brief testing with Portal & DOTA2<br>
<br>
Jordan Justen (13):<br>
i965: init global state first in<br>
brw_workaround_depthstencil_alignment<br>
gen7 depth surface: calculate more specific surface type<br>
gen7 depth surface: calculate depth (array size) for depth surface<br>
gen7 depth surface: calculate LOD being rendered to<br>
gen7 depth surface: calculate minimum array element being rendered<br>
gen7 blorp depth: calculate base surface width/height<br>
hsw hiz: Add new size restrictions for miplevels > 0<br>
gen7 fbo: make unmatched depth/stencil configs return unsupported<br>
gen7 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surface<br>
hsw hiz: Remove x/y offset restriction for hiz<br>
i965 gen7: don't set FORCE_ZERO_RTAINDEX for layered rendering<br>
intel_mipmap_tree: all layers need hiz resolves with layered<br>
rendering<br>
intel: enable GL_AMD_vertex_shader_layer extension for gen7+<br>
<br>
src/mesa/drivers/dri/i965/brw_misc_state.c | 25 +++++--<br>
src/mesa/drivers/dri/i965/brw_tex_layout.c | 10 +--<br>
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 100 +++++++++++++------------<br>
src/mesa/drivers/dri/i965/gen7_clip_state.c | 2 +-<br>
src/mesa/drivers/dri/i965/gen7_misc_state.c | 83 ++++++++++++++++++--<br>
src/mesa/drivers/dri/i965/intel_extensions.c | 4 +<br>
src/mesa/drivers/dri/i965/intel_fbo.c | 16 ++++<br>
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 61 ++++++++-------<br>
8 files changed, 203 insertions(+), 98 deletions(-)<br>
<span><font color="#888888"><br>
--<br>
1.7.10.4<br>
<br>
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