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<div class="moz-cite-prefix">Actually Type 2 packets are handled
much faster on the R6xx compared to most type 3 packets, cause
they are handled by the PFP/fetch hw and doesn't need to be
forwarded to the ME.<br>
<br>
Christian.<br>
<br>
Am 06.09.2013 02:31, schrieb Dominik Behr:<br>
</div>
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cite="mid:CABUrSUDkEkRJiLZ-SFM8YWs6rpj9GqYLYWM00Ryt5=ZOPKy8BQ@mail.gmail.com"
type="cite">
<div dir="ltr">0x80000000 is Type 2 NOP.
<div>You could make it a little better/faster by inserting
single multi-DWORD Type 3 NOP</div>
<div>And pad to 8 DWORDs. CP fetches are 32 bytes each and R600
has requires padding. Same with padding CP ring buffer updates
to 32 bytes (pad to 32bytes before you update CP_RB_WPTR).</div>
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<div class="gmail_extra"><br>
<br>
<div class="gmail_quote">On Thu, Sep 5, 2013 at 3:56 PM, Marek
Olšák <span dir="ltr"><<a moz-do-not-send="true"
href="mailto:maraeo@gmail.com" target="_blank">maraeo@gmail.com</a>></span>
wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex">
Reviewed-by: Marek Olšák <<a moz-do-not-send="true"
href="mailto:marek.olsak@amd.com">marek.olsak@amd.com</a>><br>
<br>
Though I'm not sure if 0x80000000 is correct.<br>
<span class="HOEnZb"><font color="#888888"><br>
Marek<br>
</font></span>
<div class="HOEnZb">
<div class="h5"><br>
On Wed, Sep 4, 2013 at 11:55 PM, Alex Deucher <<a
moz-do-not-send="true"
href="mailto:alexdeucher@gmail.com">alexdeucher@gmail.com</a>>
wrote:<br>
> IBs need to be a multiple of 4 dwords on r6xx asics<br>
> to avoid a hw bug.<br>
><br>
> Signed-off-by: Alex Deucher <<a
moz-do-not-send="true"
href="mailto:alexander.deucher@amd.com">alexander.deucher@amd.com</a>><br>
> CC: "9.2" <<a moz-do-not-send="true"
href="mailto:mesa-stable@lists.freedesktop.org">mesa-stable@lists.freedesktop.org</a>><br>
> CC: "9.1" <<a moz-do-not-send="true"
href="mailto:mesa-stable@lists.freedesktop.org">mesa-stable@lists.freedesktop.org</a>><br>
> ---<br>
> src/gallium/drivers/r600/r600_hw_context.c | 13
+++++++++++++<br>
> 1 file changed, 13 insertions(+)<br>
><br>
> diff --git
a/src/gallium/drivers/r600/r600_hw_context.c
b/src/gallium/drivers/r600/r600_hw_context.c<br>
> index 97b0f9c..0a219af 100644<br>
> --- a/src/gallium/drivers/r600/r600_hw_context.c<br>
> +++ b/src/gallium/drivers/r600/r600_hw_context.c<br>
> @@ -347,6 +347,19 @@ void r600_context_flush(struct
r600_context *ctx, unsigned flags)<br>
> flags |=
RADEON_FLUSH_KEEP_TILING_FLAGS;<br>
> }<br>
><br>
> + /* Pad the GFX CS to a multiple of 4 dwords
on rv6xx<br>
> + * to avoid a hw bug.<br>
> + */<br>
> + if (ctx->chip_class < R700) {<br>
> + unsigned i;<br>
> + unsigned padding_dw = 4 -
cs->cdw % 4;<br>
> + if (padding_dw < 4) {<br>
> + for (i = 0; i <
padding_dw; i++) {<br>
> +
cs->buf[cs->cdw++] = 0x80000000;<br>
> + }<br>
> + }<br>
> + }<br>
> +<br>
> /* Flush the CS. */<br>
>
ctx->ws->cs_flush(ctx->rings.gfx.cs, flags,
ctx->screen->cs_count++);<br>
> }<br>
> --<br>
> 1.8.3.1<br>
><br>
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