<div dir="ltr">On 16 September 2013 09:38, Eric Anholt <span dir="ltr"><<a href="mailto:eric@anholt.net" target="_blank">eric@anholt.net</a>></span> wrote:<br><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<div class=""><div class="h5">Kenneth Graunke <<a href="mailto:kenneth@whitecape.org">kenneth@whitecape.org</a>> writes:<br>
<br>
> This was an embarassingly large amount of copy and pasted code,<br>
> and it wasn't particularly simple code either. By factoring it out<br>
> into a helper function, we consolidate the complexity.<br>
><br>
> Signed-off-by: Kenneth Graunke <<a href="mailto:kenneth@whitecape.org">kenneth@whitecape.org</a>><br>
> ---<br>
> src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 144 +++++++++-------------<br>
> 1 file changed, 58 insertions(+), 86 deletions(-)<br>
><br>
> diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c<br>
> index 37e3174..8413308 100644<br>
> --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c<br>
> +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c<br>
> @@ -224,6 +224,37 @@ gen7_check_surface_setup(uint32_t *surf, bool is_render_target)<br>
> }<br>
> }<br>
><br>
> +static void<br>
> +gen7_emit_buffer_surface_state(struct brw_context *brw,<br>
> + uint32_t *out_offset,<br>
> + drm_intel_bo *bo,<br>
> + unsigned buffer_offset,<br>
> + unsigned surface_format,<br>
> + unsigned buffer_size,<br>
> + unsigned pitch,<br>
> + unsigned mocs)<br>
> +{<br>
> + uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,<br>
> + 8 * 4, 32, out_offset);<br>
> + memset(surf, 0, 8 * 4);<br>
> +<br>
> + surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |<br>
> + surface_format << BRW_SURFACE_FORMAT_SHIFT |<br>
> + BRW_SURFACE_RC_READ_WRITE;<br>
> + surf[1] = bo->offset + buffer_offset; /* reloc */<br>
> + surf[2] = SET_FIELD(buffer_size & 0x7f, GEN7_SURFACE_WIDTH) |<br>
> + SET_FIELD((buffer_size >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);<br>
> + surf[3] = SET_FIELD((buffer_size >> 21) & 0x3f, BRW_SURFACE_DEPTH) |<br>
> + (pitch - 1);<br>
> + surf[4] = 0;<br>
> + surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS);<br>
> +<br>
> + /* Emit relocation to surface contents */<br>
> + drm_intel_bo_emit_reloc(brw-><a href="http://batch.bo" target="_blank">batch.bo</a>, *out_offset + 4,<br>
> + bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER, 0);<br>
<br>
</div></div>I think this will segfault if BO is NULL<br>
<div><div class="h5"><br>
> +<br>
> + gen7_check_surface_setup(surf, false /* is_render_target */);<br>
> +}<br>
><br>
> static void<br>
> gen7_update_buffer_texture_surface(struct gl_context *ctx,<br>
> @@ -237,39 +268,23 @@ gen7_update_buffer_texture_surface(struct gl_context *ctx,<br>
> drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;<br>
> gl_format format = tObj->_BufferObjectFormat;<br>
><br>
> - uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,<br>
> - 8 * 4, 32, surf_offset);<br>
> - memset(surf, 0, 8 * 4);<br>
> -<br>
> uint32_t surface_format = brw_format_for_mesa_format(format);<br>
> if (surface_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {<br>
> _mesa_problem(NULL, "bad format %s for texture buffer\n",<br>
> _mesa_get_format_name(format));<br>
> }<br>
><br>
> - surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |<br>
> - surface_format << BRW_SURFACE_FORMAT_SHIFT |<br>
> - BRW_SURFACE_RC_READ_WRITE;<br>
> -<br>
> - if (bo) {<br>
> - surf[1] = bo->offset; /* reloc */<br>
> -<br>
> - drm_intel_bo_emit_reloc(brw-><a href="http://batch.bo" target="_blank">batch.bo</a>,<br>
> - *surf_offset + 4,<br>
> - bo, 0,<br>
> - I915_GEM_DOMAIN_SAMPLER, 0);<br>
> -<br>
> - int texel_size = _mesa_get_format_bytes(format);<br>
> - int w = intel_obj->Base.Size / texel_size;<br>
> -<br>
> - /* note that these differ from GEN6 */<br>
> - surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) | /* bits 6:0 of size */<br>
> - SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT); /* 20:7 */<br>
> - surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH) | /* bits 26:21 */<br>
> - (texel_size - 1);<br>
> - }<br>
> -<br>
> - gen7_check_surface_setup(surf, false /* is_render_target */);<br>
> + int texel_size = _mesa_get_format_bytes(format);<br>
> + int w = intel_obj ? intel_obj->Base.Size / texel_size : 0;<br>
> +<br>
> + gen7_emit_buffer_surface_state(brw,<br>
> + surf_offset,<br>
> + bo,<br>
> + 0,<br>
> + surface_format,<br>
> + w,<br>
> + texel_size,<br>
> + 0 /* mocs */);<br>
<br>
</div></div>But here you might pass in a NULL bo. Same for patch 4. I'm confused<br>
that this didn't produce a piglit regression.<br>
<br>
> }<br>
<br>
I think the savings is well worth it in patches 1, 3, and 4, but I'm not<br>
a fan of patch 2. I've got a lot of branches outstanding where I'm<br>
trying to finally finish off mt->first_level and the tile offset usage,<br>
and sharing code between renderbuffers and textures is just going to<br>
make that harder to do. (I'm already really tempted to split gen4/5<br>
>From gen6 RB setup, since I think I could land gen4/5 without<br>
regressing, while gen6 is the unstable hw)<br></blockquote><div><br></div><div>I really like patch 2 and would like to see it land. Can you expand on why it would complicate your work with mt->first_level and tile offset usage? AFAICT, the first_level stuff doesn't really seem to be affected by patch 2 (it's just moved from a subexpression in surf[5] to a parameter on gen7_emit_image_surface_state()), and the tile offset logic has already been removed from gen7, so it should be unrelated to patch 2.<br>
</div></div></div></div>