<p dir="ltr"><br>
On Oct 2, 2013 9:29 PM, "Francisco Jerez" <<a href="mailto:currojerez@riseup.net">currojerez@riseup.net</a>> wrote:<br>
><br>
> The maximum number of atomic buffer objects is somewhat arbitrary, we<br>
> can change it in the future easily if it turns out it's not enough...<br>
><br>
> v2: Add comments with the relevant mesa dirty bits.  Fix usage of<br>
>     BRW_NEW_UNIFORM_BUFFER in the GS ABO state atom.<br>
> v3: Update binding table layout diagrams.<br>
><br>
> Reviewed-by: Paul Berry <<a href="mailto:stereotype441@gmail.com">stereotype441@gmail.com</a>><br>
Hi,<br>
I guess this patch also depends on pending patches, right?<br>
Aiaiai-mesa fails to built it:<br></p>
<p dir="ltr">On Oct 2, 2013 9:39 PM, "Aiaiai" <aiaiai@aiaiai.ku> wrote:<br>
Hi,</p>
<p dir="ltr">I have tested your changes:</p>
<p dir="ltr">[Mesa-dev] [PATCH] i965: Implement ABO surface state emission.</p>
<p dir="ltr">Project: mesa (Mesa build tests)</p>
<p dir="ltr">Configurations: android linux</p>
<p dir="ltr">================================================================================<br>
Tested the patch(es) on top of the following commits:<br>
4e4c32b r600/llvm: Adds support for MSAA<br>
8edbd76 r600g/llvm: Undef z and w component of 2D TXP inst<br>
9f183eb r600g/llvm: fix txq for texture buffer<br>
848c0e7 i965: compute DDX in a subspan based only on top row<br>
72edba1 i965/blorp: Use passed in framebuffer rather than ctx->DrawBuffer<br>
ef8cc3e ralloc: Remove the rzalloc-based new/delete operator definition macro.<br>
fcbbecb st/mesa: Switch glsl_to_tgsi_instruction to the non-zeroing allocator.</p>
<p dir="ltr">================================================================================<br>
Failed to build for "android""</p>
<p dir="ltr">4e4c32b r600/llvm: Adds support for MSAA<br>
8edbd76 r600g/llvm: Undef z and w component of 2D TXP inst<br>
9f183eb r600g/llvm: fix txq for texture buffer<br>
848c0e7 i965: compute DDX in a subspan based only on top row<br>
72edba1 i965/blorp: Use passed in framebuffer rather than ctx->DrawBuffer<br>
ef8cc3e ralloc: Remove the rzalloc-based new/delete operator definition macro.<br>
fcbbecb st/mesa: Switch glsl_to_tgsi_instruction to the non-zeroing allocator.<br>
src/mesa/drivers/dri/i965/brw_state_dump.c:423:63: warning: pointer of type 'void *' used in arithmetic [-Wpointer-arith]<br>
src/mesa/drivers/dri/i965/brw_state_dump.c: In function 'dump_vs_constants':<br>
src/mesa/drivers/dri/i965/brw_state_dump.c:435:47: warning: pointer of type 'void *' used in arithmetic [-Wpointer-arith]<br>
src/mesa/drivers/dri/i965/brw_state_dump.c:436:45: warning: pointer of type 'void *' used in arithmetic [-Wpointer-arith]<br>
src/mesa/drivers/dri/i965/brw_state_dump.c: In function 'dump_wm_constants':<br>
src/mesa/drivers/dri/i965/brw_state_dump.c:451:47: warning: pointer of type 'void *' used in arithmetic [-Wpointer-arith]<br>
src/mesa/drivers/dri/i965/brw_state_dump.c:452:45: warning: pointer of type 'void *' used in arithmetic [-Wpointer-arith]<br>
src/mesa/drivers/dri/i965/brw_state_dump.c: In function 'dump_binding_table':<br>
src/mesa/drivers/dri/i965/brw_state_dump.c:468:44: warning: pointer of type 'void *' used in arithmetic [-Wpointer-arith]<br>
src/mesa/drivers/dri/i965/brw_state_dump.c: In function 'dump_prog_cache':<br>
src/mesa/drivers/dri/i965/brw_state_dump.c:495:33: warning: pointer of type 'void *' used in arithmetic [-Wpointer-arith]<br>
src/mesa/drivers/dri/i965/brw_vs_surface_state.c: In function 'brw_upload_vec4_pull_constants':<br>
src/mesa/drivers/dri/i965/brw_vs_surface_state.c:72:45: warning: pointer of type 'void *' used in arithmetic [-Wpointer-arith]<br>
src/mesa/drivers/dri/i965/brw_wm_surface_state.c: In function 'brw_upload_abo_surfaces':<br>
src/mesa/drivers/dri/i965/brw_wm_surface_state.c:842:28: error: 'struct gl_shader_program' has no member named 'NumAtomicBuffers'<br>
src/mesa/drivers/dri/i965/brw_wm_surface_state.c:844:14: error: 'struct gl_context' has no member named 'AtomicBufferBindings'<br>
src/mesa/drivers/dri/i965/brw_wm_surface_state.c:844:41: error: 'struct gl_shader_program' has no member named 'AtomicBuffers'<br>
src/mesa/drivers/dri/i965/brw_wm_surface_state.c:846:37: error: dereferencing pointer to incomplete type<br>
src/mesa/drivers/dri/i965/brw_wm_surface_state.c:850:16: error: 'struct <anonymous>' has no member named 'create_raw_surface'<br>
src/mesa/drivers/dri/i965/brw_wm_surface_state.c:850:52: error: dereferencing pointer to incomplete type<br>
src/mesa/drivers/dri/i965/brw_wm_surface_state.c:851:54: error: dereferencing pointer to incomplete type<br>
src/mesa/drivers/dri/i965/brw_wm_surface_state.c:855:12: error: 'struct gl_shader_program' has no member named 'NumAtomicBuffers'<br>
make: *** [out/target/product/samsungxe700t/obj/SHARED_LIBRARIES/i965_dri_intermediates/brw_wm_surface_state.o] Error 1<br>
FAILURE</p>
<p dir="ltr">================================<br></p>
<p dir="ltr">> ---<br>
>  src/mesa/drivers/dri/i965/brw_context.h          | 27 ++++++++++++--<br>
>  src/mesa/drivers/dri/i965/brw_gs_surface_state.c | 21 +++++++++++<br>
>  src/mesa/drivers/dri/i965/brw_state.h            |  3 ++<br>
>  src/mesa/drivers/dri/i965/brw_state_upload.c     |  4 +++<br>
>  src/mesa/drivers/dri/i965/brw_vs_surface_state.c | 21 +++++++++++<br>
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 45 ++++++++++++++++++++++++<br>
>  6 files changed, 119 insertions(+), 2 deletions(-)<br>
><br>
> diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h<br>
> index 3922705..1407f20 100644<br>
> --- a/src/mesa/drivers/dri/i965/brw_context.h<br>
> +++ b/src/mesa/drivers/dri/i965/brw_context.h<br>
> @@ -158,6 +158,7 @@ enum brw_state_id {<br>
>     BRW_STATE_RASTERIZER_DISCARD,<br>
>     BRW_STATE_STATS_WM,<br>
>     BRW_STATE_UNIFORM_BUFFER,<br>
> +   BRW_STATE_ATOMIC_BUFFER,<br>
>     BRW_STATE_META_IN_PROGRESS,<br>
>     BRW_STATE_INTERPOLATION_MAP,<br>
>     BRW_STATE_PUSH_CONSTANT_ALLOCATION,<br>
> @@ -196,6 +197,7 @@ enum brw_state_id {<br>
>  #define BRW_NEW_RASTERIZER_DISCARD     (1 << BRW_STATE_RASTERIZER_DISCARD)<br>
>  #define BRW_NEW_STATS_WM               (1 << BRW_STATE_STATS_WM)<br>
>  #define BRW_NEW_UNIFORM_BUFFER          (1 << BRW_STATE_UNIFORM_BUFFER)<br>
> +#define BRW_NEW_ATOMIC_BUFFER           (1 << BRW_STATE_ATOMIC_BUFFER)<br>
>  #define BRW_NEW_META_IN_PROGRESS        (1 << BRW_STATE_META_IN_PROGRESS)<br>
>  #define BRW_NEW_INTERPOLATION_MAP       (1 << BRW_STATE_INTERPOLATION_MAP)<br>
>  #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1 << BRW_STATE_PUSH_CONSTANT_ALLOCATION)<br>
> @@ -599,6 +601,12 @@ struct brw_gs_prog_data<br>
>  /** Max number of render targets in a shader */<br>
>  #define BRW_MAX_DRAW_BUFFERS 8<br>
><br>
> +/** Max number of uniform buffer objects in a shader */<br>
> +#define BRW_MAX_UBO 12<br>
> +<br>
> +/** Max number of atomic counter buffer objects in a shader */<br>
> +#define BRW_MAX_ABO 4<br>
> +<br>
>  /**<br>
>   * Max number of binding table entries used for stream output.<br>
>   *<br>
> @@ -661,6 +669,11 @@ struct brw_gs_prog_data<br>
>   *    |   : |     :                   |<br>
>   *    |  36 | UBO 11                  |<br>
>   *    +-------------------------------+<br>
> + *    |  37 | ABO 0                   |<br>
> + *    |   . |     .                   |<br>
> + *    |   : |     :                   |<br>
> + *    |  40 | ABO 3                   |<br>
> + *    +-------------------------------+<br>
>   *<br>
>   * Our VS (and Gen7 GS) binding tables are programmed as follows:<br>
>   *<br>
> @@ -677,6 +690,11 @@ struct brw_gs_prog_data<br>
>   *    |   : |     :                   |<br>
>   *    |  28 | UBO 11                  |<br>
>   *    +-------------------------------+<br>
> + *    |  29 | ABO 0                   |<br>
> + *    |   . |     .                   |<br>
> + *    |   : |     :                   |<br>
> + *    |  32 | ABO 3                   |<br>
> + *    +-------------------------------+<br>
>   *<br>
>   * Our (gen6) GS binding tables are programmed as follows:<br>
>   *<br>
> @@ -691,14 +709,16 @@ struct brw_gs_prog_data<br>
>  #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)<br>
>  #define SURF_INDEX_TEXTURE(t)        (BRW_MAX_DRAW_BUFFERS + 2 + (t))<br>
>  #define SURF_INDEX_WM_UBO(u)         (SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT) + u)<br>
> -#define SURF_INDEX_WM_SHADER_TIME    (SURF_INDEX_WM_UBO(12))<br>
> +#define SURF_INDEX_WM_ABO(a)         (SURF_INDEX_WM_UBO(BRW_MAX_UBO) + a)<br>
> +#define SURF_INDEX_WM_SHADER_TIME    (SURF_INDEX_WM_ABO(BRW_MAX_ABO))<br>
>  /** Maximum size of the binding table. */<br>
>  #define BRW_MAX_WM_SURFACES          (SURF_INDEX_WM_SHADER_TIME + 1)<br>
><br>
>  #define SURF_INDEX_VEC4_CONST_BUFFER (0)<br>
>  #define SURF_INDEX_VEC4_TEXTURE(t)   (SURF_INDEX_VEC4_CONST_BUFFER + 1 + (t))<br>
>  #define SURF_INDEX_VEC4_UBO(u)       (SURF_INDEX_VEC4_TEXTURE(BRW_MAX_TEX_UNIT) + u)<br>
> -#define SURF_INDEX_VEC4_SHADER_TIME  (SURF_INDEX_VEC4_UBO(12))<br>
> +#define SURF_INDEX_VEC4_ABO(a)       (SURF_INDEX_VEC4_UBO(BRW_MAX_UBO) + a)<br>
> +#define SURF_INDEX_VEC4_SHADER_TIME  (SURF_INDEX_VEC4_ABO(BRW_MAX_ABO))<br>
>  #define BRW_MAX_VEC4_SURFACES        (SURF_INDEX_VEC4_SHADER_TIME + 1)<br>
><br>
>  #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)<br>
> @@ -1498,6 +1518,9 @@ brw_update_sol_surface(struct brw_context *brw,<br>
>  void brw_upload_ubo_surfaces(struct brw_context *brw,<br>
>                              struct gl_shader *shader,<br>
>                              uint32_t *surf_offsets);<br>
> +void brw_upload_abo_surfaces(struct brw_context *brw,<br>
> +                             struct gl_shader_program *prog,<br>
> +                             uint32_t *surf_offsets);<br>
><br>
>  /* brw_surface_formats.c */<br>
>  bool brw_is_hiz_depth_format(struct brw_context *ctx, gl_format format);<br>
> diff --git a/src/mesa/drivers/dri/i965/brw_gs_surface_state.c b/src/mesa/drivers/dri/i965/brw_gs_surface_state.c<br>
> index d0ce412..05f9efa 100644<br>
> --- a/src/mesa/drivers/dri/i965/brw_gs_surface_state.c<br>
> +++ b/src/mesa/drivers/dri/i965/brw_gs_surface_state.c<br>
> @@ -87,3 +87,24 @@ const struct brw_tracked_state brw_gs_ubo_surfaces = {<br>
>     },<br>
>     .emit = brw_upload_gs_ubo_surfaces,<br>
>  };<br>
> +<br>
> +static void<br>
> +brw_upload_gs_abo_surfaces(struct brw_context *brw)<br>
> +{<br>
> +   struct gl_context *ctx = &brw->ctx;<br>
> +   /* _NEW_PROGRAM */<br>
> +   struct gl_shader_program *prog = ctx->Shader.CurrentGeometryProgram;<br>
> +<br>
> +   if (prog)<br>
> +      brw_upload_abo_surfaces(<br>
> +         brw, prog, &brw->gs.base.surf_offset[SURF_INDEX_VEC4_ABO(0)]);<br>
> +}<br>
> +<br>
> +const struct brw_tracked_state brw_gs_abo_surfaces = {<br>
> +   .dirty = {<br>
> +      .mesa = _NEW_PROGRAM,<br>
> +      .brw = BRW_NEW_BATCH | BRW_NEW_ATOMIC_BUFFER,<br>
> +      .cache = 0,<br>
> +   },<br>
> +   .emit = brw_upload_gs_abo_surfaces,<br>
> +};<br>
> diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h<br>
> index ec64328..ed8ce33 100644<br>
> --- a/src/mesa/drivers/dri/i965/brw_state.h<br>
> +++ b/src/mesa/drivers/dri/i965/brw_state.h<br>
> @@ -71,7 +71,9 @@ extern const struct brw_tracked_state brw_vs_prog;<br>
>  extern const struct brw_tracked_state brw_vs_samplers;<br>
>  extern const struct brw_tracked_state brw_gs_samplers;<br>
>  extern const struct brw_tracked_state brw_vs_ubo_surfaces;<br>
> +extern const struct brw_tracked_state brw_vs_abo_surfaces;<br>
>  extern const struct brw_tracked_state brw_gs_ubo_surfaces;<br>
> +extern const struct brw_tracked_state brw_gs_abo_surfaces;<br>
>  extern const struct brw_tracked_state brw_vs_unit;<br>
>  extern const struct brw_tracked_state brw_gs_prog;<br>
>  extern const struct brw_tracked_state brw_wm_prog;<br>
> @@ -81,6 +83,7 @@ extern const struct brw_tracked_state brw_wm_binding_table;<br>
>  extern const struct brw_tracked_state brw_gs_binding_table;<br>
>  extern const struct brw_tracked_state brw_vs_binding_table;<br>
>  extern const struct brw_tracked_state brw_wm_ubo_surfaces;<br>
> +extern const struct brw_tracked_state brw_wm_abo_surfaces;<br>
>  extern const struct brw_tracked_state brw_wm_unit;<br>
>  extern const struct brw_tracked_state brw_interpolation_map;<br>
><br>
> diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c<br>
> index d7fe319..64ffcd0 100644<br>
> --- a/src/mesa/drivers/dri/i965/brw_state_upload.c<br>
> +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c<br>
> @@ -204,10 +204,13 @@ static const struct brw_tracked_state *gen7_atoms[] =<br>
>      */<br>
>     &brw_vs_pull_constants,<br>
>     &brw_vs_ubo_surfaces,<br>
> +   &brw_vs_abo_surfaces,<br>
>     &brw_gs_pull_constants,<br>
>     &brw_gs_ubo_surfaces,<br>
> +   &brw_gs_abo_surfaces,<br>
>     &brw_wm_pull_constants,<br>
>     &brw_wm_ubo_surfaces,<br>
> +   &brw_wm_abo_surfaces,<br>
>     &gen6_renderbuffer_surfaces,<br>
>     &brw_texture_surfaces,<br>
>     &brw_vs_binding_table,<br>
> @@ -398,6 +401,7 @@ static struct dirty_bit_map brw_bits[] = {<br>
>     DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD),<br>
>     DEFINE_BIT(BRW_NEW_STATS_WM),<br>
>     DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER),<br>
> +   DEFINE_BIT(BRW_NEW_ATOMIC_BUFFER),<br>
>     DEFINE_BIT(BRW_NEW_META_IN_PROGRESS),<br>
>     DEFINE_BIT(BRW_NEW_INTERPOLATION_MAP),<br>
>     DEFINE_BIT(BRW_NEW_PUSH_CONSTANT_ALLOCATION),<br>
> diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c<br>
> index 2c5d06f..c6461c7 100644<br>
> --- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c<br>
> +++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c<br>
> @@ -148,3 +148,24 @@ const struct brw_tracked_state brw_vs_ubo_surfaces = {<br>
>     },<br>
>     .emit = brw_upload_vs_ubo_surfaces,<br>
>  };<br>
> +<br>
> +static void<br>
> +brw_upload_vs_abo_surfaces(struct brw_context *brw)<br>
> +{<br>
> +   struct gl_context *ctx = &brw->ctx;<br>
> +   /* _NEW_PROGRAM */<br>
> +   struct gl_shader_program *prog = ctx->Shader.CurrentVertexProgram;<br>
> +<br>
> +   if (prog)<br>
> +      brw_upload_abo_surfaces(<br>
> +         brw, prog, &brw->vs.base.surf_offset[SURF_INDEX_VEC4_ABO(0)]);<br>
> +}<br>
> +<br>
> +const struct brw_tracked_state brw_vs_abo_surfaces = {<br>
> +   .dirty = {<br>
> +      .mesa = _NEW_PROGRAM,<br>
> +      .brw = BRW_NEW_BATCH | BRW_NEW_ATOMIC_BUFFER,<br>
> +      .cache = 0,<br>
> +   },<br>
> +   .emit = brw_upload_vs_abo_surfaces,<br>
> +};<br>
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c<br>
> index 4c3eb69..70f1391 100644<br>
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c<br>
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c<br>
> @@ -833,6 +833,51 @@ const struct brw_tracked_state brw_wm_ubo_surfaces = {<br>
>  };<br>
><br>
>  void<br>
> +brw_upload_abo_surfaces(struct brw_context *brw,<br>
> +                       struct gl_shader_program *prog,<br>
> +                       uint32_t *surf_offsets)<br>
> +{<br>
> +   struct gl_context *ctx = &brw->ctx;<br>
> +<br>
> +   for (int i = 0; i < prog->NumAtomicBuffers; i++) {<br>
> +      struct gl_atomic_buffer_binding *binding =<br>
> +         &ctx->AtomicBufferBindings[prog->AtomicBuffers[i].Binding];<br>
> +      struct intel_buffer_object *intel_bo =<br>
> +         intel_buffer_object(binding->BufferObject);<br>
> +      drm_intel_bo *bo = intel_bufferobj_buffer(brw, intel_bo,<br>
> +                                                INTEL_READ | INTEL_WRITE_PART);<br>
> +<br>
> +      brw->vtbl.create_raw_surface(brw, bo, binding->Offset,<br>
> +                                   bo->size - binding->Offset,<br>
> +                                   &surf_offsets[i], true);<br>
> +   }<br>
> +<br>
> +   if (prog->NumAtomicBuffers)<br>
> +      brw->state.dirty.brw |= BRW_NEW_SURFACES;<br>
> +}<br>
> +<br>
> +static void<br>
> +brw_upload_wm_abo_surfaces(struct brw_context *brw)<br>
> +{<br>
> +   struct gl_context *ctx = &brw->ctx;<br>
> +   /* _NEW_PROGRAM */<br>
> +   struct gl_shader_program *prog = ctx->Shader._CurrentFragmentProgram;<br>
> +<br>
> +   if (prog)<br>
> +      brw_upload_abo_surfaces(<br>
> +         brw, prog, &brw->wm.base.surf_offset[SURF_INDEX_WM_ABO(0)]);<br>
> +}<br>
> +<br>
> +const struct brw_tracked_state brw_wm_abo_surfaces = {<br>
> +   .dirty = {<br>
> +      .mesa = _NEW_PROGRAM,<br>
> +      .brw = BRW_NEW_BATCH | BRW_NEW_ATOMIC_BUFFER,<br>
> +      .cache = 0,<br>
> +   },<br>
> +   .emit = brw_upload_wm_abo_surfaces,<br>
> +};<br>
> +<br>
> +void<br>
>  gen4_init_vtable_surface_functions(struct brw_context *brw)<br>
>  {<br>
>     brw->vtbl.update_texture_surface = brw_update_texture_surface;<br>
> --<br>
> 1.8.3.4<br>
><br>
> _______________________________________________<br>
> mesa-dev mailing list<br>
> <a href="mailto:mesa-dev@lists.freedesktop.org">mesa-dev@lists.freedesktop.org</a><br>
> <a href="http://lists.freedesktop.org/mailman/listinfo/mesa-dev">http://lists.freedesktop.org/mailman/listinfo/mesa-dev</a><br>
</p>