<div dir="ltr">On 14 October 2013 10:12, Anuj Phogat <span dir="ltr"><<a href="mailto:anuj.phogat@gmail.com" target="_blank">anuj.phogat@gmail.com</a>></span> wrote:<br><div class="gmail_extra"><div class="gmail_quote">
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">- Enable GEN7_WM_MSDISPMODE_PERSAMPLE, GEN7_WM_POSOFFSET_SAMPLE,<br>
GEN7_WM_OMASK_TO_RENDER_TARGET as per extension's specification.<br>
- Don't enable GEN7_WM_16_DISPATCH_ENABLE when GEN7_WM_MSDISPMODE_PERSAMPLE<br>
is enabled. Refer IVB PRM Vol. 2, Part 1, Page 288 for details.<br>
<br>
Signed-off-by: Anuj Phogat <<a href="mailto:anuj.phogat@gmail.com">anuj.phogat@gmail.com</a>><br></blockquote><div><br></div><div>My comments on patch 6 apply here as well.<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
---<br>
src/mesa/drivers/dri/i965/gen7_wm_state.c | 70 +++++++++++++++++++++++++++++--<br>
1 file changed, 67 insertions(+), 3 deletions(-)<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c<br>
index a2046c3..0267e0e 100644<br>
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c<br>
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c<br>
@@ -82,9 +82,15 @@ upload_wm_state(struct brw_context *brw)<br>
GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;<br>
<br>
/* _NEW_COLOR, _NEW_MULTISAMPLE */<br>
+ /* Enable if the pixel shader kernel generates and outputs oMask.<br>
+ */<br>
if (fp->program.UsesKill || ctx->Color.AlphaEnabled ||<br>
- ctx->Multisample.SampleAlphaToCoverage)<br>
+ ctx->Multisample.SampleAlphaToCoverage ||<br>
+ (ctx->Multisample.SampleShading &&<br>
+ (fp->program.Base.OutputsWritten &<br>
+ BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK)))) {<br>
dw1 |= GEN7_WM_KILL_ENABLE;<br>
+ }<br>
<br>
/* _NEW_BUFFERS */<br>
if (brw_color_buffer_write_enabled(brw) || writes_depth ||<br>
@@ -97,7 +103,25 @@ upload_wm_state(struct brw_context *brw)<br>
dw1 |= GEN7_WM_MSRAST_ON_PATTERN;<br>
else<br>
dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;<br>
- dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;<br>
+ /* From arb_sample_shading specification:<br>
+ * "If MULTISAMPLE or SAMPLE_SHADING_ARB is disabled, sample shading<br>
+ * has no effect."<br>
+ *<br>
+ * "Using gl_SampleID in a fragment shader causes the entire shader<br>
+ * to be evaluated per-sample."<br>
+ * "Using gl_SamplePosition in a fragment shader causes the entire<br>
+ * shader to be evaluated per-sample."<br>
+ *<br>
+ * I interprate the above four lines as enable the sample shading<br>
+ * if fragment shader uses gl_SampleID or gl_SamplePosition.<br>
+ */<br>
+ if (ctx->Multisample.Enabled &&<br>
+ (ctx->Multisample.SampleShading ||<br>
+ brw->fragment_program->Base.InputsRead & VARYING_BIT_SAMPLE_ID ||<br>
+ brw->fragment_program->Base.InputsRead & VARYING_BIT_SAMPLE_POS))<br>
+ dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;<br>
+ else<br>
+ dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;<br>
} else {<br>
dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;<br>
dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;<br>
@@ -129,6 +153,8 @@ upload_ps_state(struct brw_context *brw)<br>
uint32_t dw2, dw4, dw5;<br>
const int max_threads_shift = brw->is_haswell ?<br>
HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;<br>
+ bool msdispmode_persample = false;<br>
+ bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1;<br>
<br>
/* BRW_NEW_PS_BINDING_TABLE */<br>
BEGIN_BATCH(2);<br>
@@ -169,6 +195,34 @@ upload_ps_state(struct brw_context *brw)<br>
if (brw->wm.prog_data->nr_params > 0)<br>
dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;<br>
<br>
+ /* From the IVB PRM, volume 2 part 1, page 287:<br>
+ * "This bit is inserted in the PS payload header and made available to<br>
+ * the DataPort (either via the message header or via header bypass) to<br>
+ * indicate that oMask data (one or two phases) is included in Render<br>
+ * Target Write messages. If present, the oMask data is used to mask off<br>
+ * samples."<br>
+ */<br>
+ if (ctx->Extensions.ARB_sample_shading &&<br>
+ (brw->fragment_program->Base.OutputsWritten &<br>
+ BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK)))<br>
+ dw4 |= GEN7_PS_OMASK_TO_RENDER_TARGET;<br>
+<br>
+ /* From the IVB PRM, volume 2 part 1, page 287:<br>
+ * "If the PS kernel does not need the Position XY Offsets to<br>
+ * compute a Position Value, then this field should be programmed<br>
+ * to POSOFFSET_NONE."<br>
+ * "SW Recommendation: If the PS kernel needs the Position Offsets<br>
+ * to compute a Position XY value, this field should match Position<br>
+ * ZW Interpolation Mode to ensure a consistent position.xyzw<br>
+ * computation."<br>
+ * We only require XY sample offsets. So, this recommendation doesn't<br>
+ * look useful at the moment. We might need this in future.<br>
+ */<br>
+ if (brw->fragment_program->Base.InputsRead & VARYING_BIT_SAMPLE_POS)<br>
+ dw4 |= GEN7_PS_POSOFFSET_SAMPLE;<br>
+ else<br>
+ dw4 |= GEN7_PS_POSOFFSET_NONE;<br>
+<br>
/* CACHE_NEW_WM_PROG | _NEW_COLOR<br>
*<br>
* The hardware wedges if you have this bit set but don't turn on any dual<br>
@@ -185,7 +239,17 @@ upload_ps_state(struct brw_context *brw)<br>
dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;<br>
<br>
dw4 |= GEN7_PS_8_DISPATCH_ENABLE;<br>
- if (brw->wm.prog_data->prog_offset_16)<br>
+ msdispmode_persample =<br>
+ ctx->Multisample.Enabled &&<br>
+ (ctx->Multisample.SampleShading ||<br>
+ brw->fragment_program->Base.InputsRead & VARYING_BIT_SAMPLE_ID ||<br>
+ brw->fragment_program->Base.InputsRead & VARYING_BIT_SAMPLE_POS);<br>
+<br>
+ /* In case of non 1x (i.e 4x, 8x) multisampling with MDISPMODE_PERSAMPLE,<br>
+ * only one of SIMD8 and SIMD16 should be enabled.<br>
+ */<br>
+ if (brw->wm.prog_data->prog_offset_16 &&<br>
+ !(multisampled_fbo && msdispmode_persample))<br>
dw4 |= GEN7_PS_16_DISPATCH_ENABLE;<br>
<br>
dw5 |= (brw->wm.prog_data->first_curbe_grf <<<br>
<span class="HOEnZb"><font color="#888888">--<br>
1.8.1.4<br>
<br>
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</font></span></blockquote></div><br></div></div>