<div dir="ltr">On 25 October 2013 16:45, Anuj Phogat <<a href="mailto:anuj.phogat@gmail.com" target="_blank">anuj.phogat@gmail.com</a>> wrote: <div class="gmail_extra"><div class="gmail_quote"> <blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">V2: - Update comments. - Make changes to support simd16 mode. - Add compute_pos_offset variable in brw_wm_prog_key. - Add variable uses_omask in brw_wm_prog_data. Signed-off-by: Anuj Phogat <<a href="mailto:anuj.phogat@gmail.com">anuj.phogat@gmail.com</a>> --- src/mesa/drivers/dri/i965/brw_context.h | 1 + src/mesa/drivers/dri/i965/brw_fs.cpp | 65 ++++++++++++++++++++++++++++ src/mesa/drivers/dri/i965/brw_fs.h | 2 + src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 5 +++ src/mesa/drivers/dri/i965/brw_wm.c | 6 +++ src/mesa/drivers/dri/i965/brw_wm.h | 2 + 6 files changed, 81 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 3b95922..d16f257 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -380,6 +380,7 @@ struct brw_wm_prog_data { GLuint nr_params; /**< number of float params/constants */ GLuint nr_pull_params; bool dual_src_blend; + bool uses_pos_offset; uint32_t prog_offset_16; /** diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 65a4b66..0f8213e 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -1118,6 +1118,64 @@ fs_visitor::emit_frontfacing_interpolation(ir_variable *ir) return reg; } +void +fs_visitor::compute_sample_position(fs_reg dst, fs_reg int_sample_pos) +{ + assert(dst.type == BRW_REGISTER_TYPE_F); + + if (c->key.compute_pos_offset) { + /* Convert int_sample_pos to floating point */ + emit(MOV(dst, int_sample_pos)); + /* Scale to the range [0, 1] */ + emit(MUL(dst, dst, fs_reg(1 / 16.0f))); + } + else { + /* From ARB_sample_shading specification: + * "When rendering to a non-multisample buffer, or if multisample + * rasterization is disabled, gl_SamplePosition will always be + * (0.5, 0.5). + */ + emit(MOV(dst, fs_reg(0.5f))); + } +} + +fs_reg * +fs_visitor::emit_samplepos_setup(ir_variable *ir) +{ + assert(brw->gen >= 6); + assert(ir->type == glsl_type::vec2_type); + + this->current_annotation = "compute sample position"; + fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); + fs_reg pos = *reg; + fs_reg int_sample_x = fs_reg(this, glsl_type::int_type); + fs_reg int_sample_y = fs_reg(this, glsl_type::int_type); + + /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16 + * mode will be enabled. + * + * From the Ivy Bridge PRM, volume 2 part 1, page 344: + * R31.1:0 Position Offset X/Y for Slot[3:0] + * R31.3:2 Position Offset X/Y for Slot[7:4] + * ..... + * + * The X, Y sample positions come in as bytes in thread payload. So, read + * the positions using vstride=16, width=8, hstride=2. + */ + struct brw_reg sample_pos_reg = + stride(retype(brw_vec1_grf(c->sample_pos_reg, 0), + BRW_REGISTER_TYPE_B), 16, 8, 2); + + emit(MOV(int_sample_x, fs_reg(sample_pos_reg))); + /* Compute gl_SamplePosition.x */ + compute_sample_position(pos, int_sample_x); + pos.reg_offset += dispatch_width / 8; + emit(MOV(int_sample_y, fs_reg(suboffset(sample_pos_reg, 1)))); + /* Compute gl_SamplePosition.y */ + compute_sample_position(pos, int_sample_y); + return reg; +} + fs_reg fs_visitor::fix_math_operand(fs_reg src) { @@ -2985,7 +3043,14 @@ fs_visitor::setup_payload_gen6() c->nr_payload_regs++; } } + + c->prog_data.uses_pos_offset = c->key.compute_pos_offset; /* R31: MSAA position offsets. */ + if (c->prog_data.uses_pos_offset) { + c->sample_pos_reg = c->nr_payload_regs; + c->nr_payload_regs++; + } + /* R32-: bary for 32-pixel. */ /* R58-59: interp W for 32-pixel. */ diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index b5aed23..db5df39 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -333,9 +333,11 @@ public: glsl_interp_qualifier interpolation_mode, bool is_centroid); fs_reg *emit_frontfacing_interpolation(ir_variable *ir); + fs_reg *emit_samplepos_setup(ir_variable *ir); fs_reg *emit_general_interpolation(ir_variable *ir); void emit_interpolation_setup_gen4(); void emit_interpolation_setup_gen6(); + void compute_sample_position(fs_reg dst, fs_reg int_sample_pos); fs_reg rescale_texcoord(ir_texture *ir, fs_reg coordinate, bool is_rect, int sampler, int texunit); fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 9f37013..51972fe 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -125,6 +125,11 @@ fs_visitor::visit(ir_variable *ir) reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); reg->type = brw_type_for_base_type(ir->type); + + } else if (ir->mode == ir_var_system_value) { + if (!strcmp(ir->name, "gl_SamplePosition")) { + reg = emit_samplepos_setup(ir); + } </blockquote><div> </div><div>Rather than do a strcmp on the name, I'd recommend just looking at ir->location. For gl_SamplePosition it will be equal to SYSTEM_VALUE_SAMPLE_POS. With that fixed, this patch is: Reviewed-by: Paul Berry <<a href="mailto:stereotype441@gmail.com">stereotype441@gmail.com</a>> </div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> } if (!reg) diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 0fda490..d2a5a9f 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -37,6 +37,7 @@ #include "main/fbobject.h" #include "main/samplerobj.h" #include "program/prog_parameter.h" +#include "program/program.h" #include "glsl/ralloc.h" @@ -483,6 +484,11 @@ static void brw_wm_populate_key( struct brw_context *brw, key->replicate_alpha = ctx->DrawBuffer->_NumColorDrawBuffers > 1 && (ctx->Multisample.SampleAlphaToCoverage || ctx->Color.AlphaEnabled); + /* _NEW_BUFFERS _NEW_MULTISAMPLE */ + key->compute_pos_offset = + _mesa_get_min_invocations_per_fragment(ctx, &fp->program) > 1 && + fp->program.Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_POS; + /* BRW_NEW_VUE_MAP_GEOM_OUT */ if (brw->gen < 6 || _mesa_bitcount_64(fp->program.Base.InputsRead & BRW_FS_VARYING_INPUT_MASK) > 16) diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index 259a4b6..eb740ad 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -65,6 +65,7 @@ struct brw_wm_prog_key { GLuint replicate_alpha:1; GLuint render_to_fbo:1; GLuint clamp_fragment_color:1; + GLuint compute_pos_offset:1; GLuint line_aa:2; GLuint high_quality_derivatives:1; @@ -83,6 +84,7 @@ struct brw_wm_compile { uint8_t source_w_reg; uint8_t aa_dest_stencil_reg; uint8_t dest_depth_reg; + uint8_t sample_pos_reg; uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT]; uint8_t nr_payload_regs; GLuint source_depth_to_render_target:1; -- 1.8.1.4 </blockquote></div> </div></div>