<div dir="ltr"><br><div class="gmail_extra"><br><br><div class="gmail_quote">On Tue, Oct 29, 2013 at 12:36 AM, Eric Anholt <span dir="ltr"><<a href="mailto:eric@anholt.net" target="_blank">eric@anholt.net</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="im">Anuj Phogat <<a href="mailto:anuj.phogat@gmail.com">anuj.phogat@gmail.com</a>> writes:<br>
<br>
> V2:<br>
> - Update comments.<br>
> - Make changes to support simd16 mode.<br>
> - Add compute_pos_offset variable in brw_wm_prog_key.<br>
> - Add variable uses_omask in brw_wm_prog_data.<br>
><br>
> Signed-off-by: Anuj Phogat <<a href="mailto:anuj.phogat@gmail.com">anuj.phogat@gmail.com</a>><br>
<br>
</div><div><div class="h5">> +fs_reg *<br>
> +fs_visitor::emit_samplepos_setup(ir_variable *ir)<br>
> +{<br>
> + assert(brw->gen >= 6);<br>
> + assert(ir->type == glsl_type::vec2_type);<br>
> +<br>
> + this->current_annotation = "compute sample position";<br>
> + fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);<br>
> + fs_reg pos = *reg;<br>
> + fs_reg int_sample_x = fs_reg(this, glsl_type::int_type);<br>
> + fs_reg int_sample_y = fs_reg(this, glsl_type::int_type);<br>
> +<br>
> + /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16<br>
> + * mode will be enabled.<br>
> + *<br>
> + * From the Ivy Bridge PRM, volume 2 part 1, page 344:<br>
> + * R31.1:0 Position Offset X/Y for Slot[3:0]<br>
> + * R31.3:2 Position Offset X/Y for Slot[7:4]<br>
> + * .....<br>
> + *<br>
> + * The X, Y sample positions come in as bytes in thread payload. So, read<br>
> + * the positions using vstride=16, width=8, hstride=2.<br>
> + */<br>
> + struct brw_reg sample_pos_reg =<br>
> + stride(retype(brw_vec1_grf(c->sample_pos_reg, 0),<br>
> + BRW_REGISTER_TYPE_B), 16, 8, 2);<br>
> +<br>
> + emit(MOV(int_sample_x, fs_reg(sample_pos_reg)));<br>
> + /* Compute gl_SamplePosition.x */<br>
> + compute_sample_position(pos, int_sample_x);<br>
> + pos.reg_offset += dispatch_width / 8;<br>
<br>
</div></div>I noticed this during a brief glance at the series: You're incrementing<br>
pos's reg_offset by 2 in the dispatch_width == 16 case, but afaik<br>
ir->type is just a vec2. If you want to access the second half of a<br>
vec2 GRF, that's just pos.reg_offset++ regardless of whether you're in 8<br>
or 16 mode.<br></blockquote><div style>Thanks for noticing this Eric. I'll fix it. Code generated for SIMD16 is still</div><div style>untested because of some unexpected issues I faced with "SIMD16 only"</div>
<div style>dispatch. That's why we're enabling 'SIMD8 only' dispatch in this series.</div><div style> </div></div><br></div></div>