<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On 26 November 2013 17:34, Chad Versace <span dir="ltr"><<a href="mailto:chad.versace@linux.intel.com" target="_blank">chad.versace@linux.intel.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">Pre-patch, the workaround was applied to only HSW GT3. However, the<br>
workaround also fixes render corruption on the HSW GT1 Chromebook,<br>
codenamed Falco.<br>
<br>
CC: Anuj Phogat <<a href="mailto:anuj.phogat@gmail.com" target="_blank">anuj.phogat@gmail.com</a>><br>
CC: Paul Berry <<a href="mailto:stereotype441@gmail.com" target="_blank">stereotype441@gmail.com</a>><br>
OTC-Tracker: CHRMOS-812<br>
Signed-off-by: Chad Versace <<a href="mailto:chad.versace@linux.intel.com" target="_blank">chad.versace@linux.intel.com</a>><br>
---<br>
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 6 +++---<br>
1 file changed, 3 insertions(+), 3 deletions(-)<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp<br>
index 63d83d7..2620ce6 100644<br>
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp<br>
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp<br>
@@ -265,7 +265,7 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct brw_context *brw,<br>
x_align *= 16;<br>
y_align *= 32;<br>
<br>
- if (brw->is_haswell && brw->gt == 3) {<br>
+ if (brw->is_haswell) {<br></blockquote><div><br></div><div>Ok, I'll ask the obvious question: if the bspec says that this extra rectangle alignment code is needed for IVB, VLVT, and HSW, why are we doing it for just HSW?</div>
<div><br></div><div>I suspect that in truth, the extra rectangle alignment is only needed for HSW (This is based in part on the fact that fast clears have been working fine on IVB for a long time without this bug fix), so the patch will probably work fine as written. But the performance cost of applying the extra alignment to IVB is minuscule, and if it saves us from having to track down and re-fix this bug one more time, it will be worth it.</div>
<div><br></div><div>On the other hand, there's some appeal to limiting the scope of the bug fix to just the hardware that's been experiencing problems.</div><div><br>
</div><div>I'll leave it up to you. Either way, the series is:</div><div><br></div><div>Reviewed-by: Paul Berry <<a href="mailto:stereotype441@gmail.com" target="_blank">stereotype441@gmail.com</a>></div><div>
<br></div><div>Note: Personally I'd prefer to see the two patches squashed together, but I won't be a stickler about that.</div><div><br></div><div>Oh, one other question: was it a deliberate decision not to mark this as a candidate for cherry-picking back to the 10.0 and 9.2 branches? At first blush it seems worth cherry-picking to me.</div>
<div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
/* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel<br>
* Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color<br>
* Clear of Non-MultiSampled Render Target Restrictions":<br>
@@ -275,8 +275,8 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct brw_context *brw,<br>
* y_align values computed above are the relevant entries in the<br>
* referred table.<br>
*<br>
- * Note: An older BSpec documented the above restriction for only<br>
- * HSW GT3.<br>
+ * Note: An older BSpec documented the above restriction for only HSW<br>
+ * GT3. However, the restriction also fixes corruption on HSW GT1.<br>
*/<br>
x0 = ROUND_DOWN_TO(x0, 2 * x_align);<br>
y0 = ROUND_DOWN_TO(y0, 2 * y_align);<br>
<span><font color="#888888">--<br>
1.8.4<br>
<br>
</font></span></blockquote></div><br></div></div>