<div dir="ltr"><div><div><div>Ken and I discussed doing this only for when mt->first_layer == mt->last_layer<br></div>and decided to try this instead. In testing, it didn't seem to impact other platforms (I used jenkins).<br><br></div>Still, after poking at this again today and talking with Jason, I think that the best long term solution is to send a v2 such as you suggested where I eliminate any chance that the user will try to create an array texture for the pbo in meta_texsubimage. This will most likely involve reverting commits such as 404660e.<br><br></div>As far as this particular patch is concerned, since it doesn't actually fix a known issue, let's discard it for now.<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Feb 23, 2015 at 11:57 AM, Neil Roberts <span dir="ltr"><<a href="mailto:neil@linux.intel.com" target="_blank">neil@linux.intel.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Is this patch no longer relevant considering the earlier patches make it<br>
no longer use array textures?<br>
<br>
Otherwise, does this work for gens other than 7? If I've understood the<br>
bspec correctly, only Gen7 has the surface array spacing option in the<br>
surface state so it's not possible to choose this layout on other gens.<br>
I think on Gen6 this layout gets chosen for you depending on certain<br>
circumstances. On Gen8+ you can get the same benefit as this layout by<br>
just picking your own qpitch value that doesn't include space for the<br>
mipmaps. I have posted a patch for Skylake which effectively implements<br>
this by using mt->total_height for the qpitch value as this will either<br>
have space for the mipmaps or not depending on the values of<br>
mt->first_level and mt->last_level.<br>
<br>
<a href="http://lists.freedesktop.org/archives/mesa-dev/2015-February/077607.html" target="_blank">http://lists.freedesktop.org/archives/mesa-dev/2015-February/077607.html</a><br>
<br>
We might want to do something like your patch for Gen7 but in<br>
intel_miptree_create_layout instead of intel_miptree_create_for_bo. We<br>
can make it pick the ALL_SLICES_AT_EACH_LOD layout whenever<br>
mt->first_level==mt->last_level in addition to the other cases where it<br>
is chosen.<br>
<br>
For Gen8 I think setting that will magically make it pick a qpitch value<br>
that will make it work, but it'd be a bit weird because it won't really<br>
be using the ALL_SLICES_AT_EACH_LOD layout and it will only be correct<br>
if there are no mipmaps. Instead it might be better to handle it<br>
directly when picking the qpitch value like the Skylake patch.<br>
<br>
Regards,<br>
- Neil<br>
<div><div class="h5"><br>
Laura Ekstrand <<a href="mailto:laura@jlekstrand.net">laura@jlekstrand.net</a>> writes:<br>
<br>
> Textures made expressly for internal buffer objects shouldn't have extra<br>
> padding around them, but should be densely packed.<br>
> ---<br>
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-<br>
> 1 file changed, 1 insertion(+), 1 deletion(-)<br>
><br>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c<br>
> index 0e3888f..b46532d 100644<br>
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c<br>
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c<br>
> @@ -724,7 +724,7 @@ intel_miptree_create_for_bo(struct brw_context *brw,<br>
> mt = intel_miptree_create_layout(brw, target, format,<br>
> 0, 0,<br>
> width, height, depth,<br>
> - true, 0, false);<br>
> + true, 0, true);<br>
> if (!mt) {<br>
> free(mt);<br>
> return mt;<br>
> --<br>
> 2.1.0<br>
><br>
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</blockquote></div><br></div>