<p dir="ltr"><br>
On Sep 11, 2015 03:25, "Eduardo Lima Mitev" <<a href="mailto:elima@igalia.com">elima@igalia.com</a>> wrote:<br>
><br>
> On 09/10/2015 02:50 AM, Jason Ekstrand wrote:<br>
> > We made this switch in the FS backend some time ago and it seems to make a<br>
> > number of things a bit easier.<br>
> ><br>
><br>
> The commit log could be a bit less abstract, like mentioning why this<br>
> change helps the subsequent passes. In any case, if it was only for<br>
> consistency with FS, this change is beneficial.<br>
><br>
> I also tested it with full dEQP GLES3 suite, apart from piglit, on HWS.<br>
> No regressions.<br>
><br>
> Reviewed-by: Eduardo Lima Mitev <<a href="mailto:elima@igalia.com">elima@igalia.com</a>></p>
<p dir="ltr">How much of this series were you planning to review? If you don't feel like you can review the whole thing (I'm reasonably confident in your ability to), I can find another person to review. I just want to know how to plan.</p>
<p dir="ltr">--Jason</p>
<p dir="ltr">> > ---<br>
> > src/mesa/drivers/dri/i965/brw_nir.c | 2 +-<br>
> > src/mesa/drivers/dri/i965/brw_vec4.h | 1 +<br>
> > src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 21 ++++++++++++++++++---<br>
> > 3 files changed, 20 insertions(+), 4 deletions(-)<br>
> ><br>
> > diff --git a/src/mesa/drivers/dri/i965/brw_nir.c b/src/mesa/drivers/dri/i965/brw_nir.c<br>
> > index 8f3edc5..f326b23 100644<br>
> > --- a/src/mesa/drivers/dri/i965/brw_nir.c<br>
> > +++ b/src/mesa/drivers/dri/i965/brw_nir.c<br>
> > @@ -183,7 +183,7 @@ brw_create_nir(struct brw_context *brw,<br>
> > nir_print_shader(nir, stderr);<br>
> > }<br>
> ><br>
> > - nir_convert_from_ssa(nir, is_scalar);<br>
> > + nir_convert_from_ssa(nir, true);<br>
> > nir_validate_shader(nir);<br>
> ><br>
> > if (!is_scalar) {<br>
> > diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h<br>
> > index 01c6e84..de74ec9 100644<br>
> > --- a/src/mesa/drivers/dri/i965/brw_vec4.h<br>
> > +++ b/src/mesa/drivers/dri/i965/brw_vec4.h<br>
> > @@ -423,6 +423,7 @@ public:<br>
> > virtual void nir_emit_alu(nir_alu_instr *instr);<br>
> > virtual void nir_emit_jump(nir_jump_instr *instr);<br>
> > virtual void nir_emit_texture(nir_tex_instr *instr);<br>
> > + virtual void nir_emit_undef(nir_ssa_undef_instr *instr);<br>
> ><br>
> > dst_reg get_nir_dest(nir_dest dest, enum brw_reg_type type);<br>
> > dst_reg get_nir_dest(nir_dest dest, nir_alu_type type);<br>
> > diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp<br>
> > index 751ec73..87a7941 100644<br>
> > --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp<br>
> > +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp<br>
> > @@ -367,6 +367,10 @@ vec4_visitor::nir_emit_instr(nir_instr *instr)<br>
> > nir_emit_texture(nir_instr_as_tex(instr));<br>
> > break;<br>
> ><br>
> > + case nir_instr_type_ssa_undef:<br>
> > + nir_emit_undef(nir_instr_as_ssa_undef(instr));<br>
> > + break;<br>
> > +<br>
> > default:<br>
> > fprintf(stderr, "VS instruction not yet implemented by NIR->vec4\n");<br>
> > break;<br>
> > @@ -393,9 +397,14 @@ dst_reg_for_nir_reg(vec4_visitor *v, nir_register *nir_reg,<br>
> > dst_reg<br>
> > vec4_visitor::get_nir_dest(nir_dest dest)<br>
> > {<br>
> > - assert(!dest.is_ssa);<br>
> > - return dst_reg_for_nir_reg(this, dest.reg.reg, dest.reg.base_offset,<br>
> > - dest.reg.indirect);<br>
> > + if (dest.is_ssa) {<br>
> > + dst_reg dst = dst_reg(GRF, alloc.allocate(1));<br>
> > + nir_ssa_values[dest.ssa.index] = dst;<br>
> > + return dst;<br>
> > + } else {<br>
> > + return dst_reg_for_nir_reg(this, dest.reg.reg, dest.reg.base_offset,<br>
> > + dest.reg.indirect);<br>
> > + }<br>
> > }<br>
> ><br>
> > dst_reg<br>
> > @@ -1528,4 +1537,10 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)<br>
> > mcs, is_cube_array, sampler, sampler_reg);<br>
> > }<br>
> ><br>
> > +void<br>
> > +vec4_visitor::nir_emit_undef(nir_ssa_undef_instr *instr)<br>
> > +{<br>
> > + nir_ssa_values[instr->def.index] = dst_reg(GRF, alloc.allocate(1));<br>
> > +}<br>
> > +<br>
> > }<br>
> ><br>
><br>
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