<div dir="ltr">Reviewed-by: Chris Forbes <<a href="mailto:chrisf@ijw.co.nz">chrisf@ijw.co.nz</a>><br></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jan 12, 2016 at 12:04 PM, Kenneth Graunke <span dir="ltr"><<a href="mailto:kenneth@whitecape.org" target="_blank">kenneth@whitecape.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">This adds barrier dependencies around TCS_OPCODE_URB_WRITE, preventing<br>
reads and writes from being incorrectly scheduled.<br>
<br>
Fixes rendering in GFXBench 4.0's tessellation demo.<br>
<br>
For some reason, we haven't ever listed URB writes as having<br>
side-effects. This hasn't been a problem because in most stages, we<br>
never read from the URB, and only write to each location once.<br>
<br>
Bugzilla: <a href="https://bugs.freedesktop.org/show_bug.cgi?id=93526" rel="noreferrer" target="_blank">https://bugs.freedesktop.org/show_bug.cgi?id=93526</a><br>
Signed-off-by: Kenneth Graunke <<a href="mailto:kenneth@whitecape.org">kenneth@whitecape.org</a>><br>
---<br>
src/mesa/drivers/dri/i965/brw_shader.cpp | 1 +<br>
1 file changed, 1 insertion(+)<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp<br>
index efc24f9..0ac3f4a 100644<br>
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp<br>
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp<br>
@@ -1022,6 +1022,7 @@ backend_instruction::has_side_effects() const<br>
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:<br>
case FS_OPCODE_FB_WRITE:<br>
case SHADER_OPCODE_BARRIER:<br>
+ case TCS_OPCODE_URB_WRITE:<br>
case TCS_OPCODE_RELEASE_INPUT:<br>
return true;<br>
default:<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.7.0<br>
<br>
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</font></span></blockquote></div><br></div>