On Jan 16, 2016 5:56 PM, "Matt Turner" <<a href="mailto:mattst88@gmail.com">mattst88@gmail.com</a>> wrote: > > On Thu, Jan 14, 2016 at 12:27 PM, Matt Turner <<a href="mailto:mattst88@gmail.com">mattst88@gmail.com</a>> wrote: > > On Thu, Jan 14, 2016 at 12:08 PM, Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>> wrote: > >> BDW adds the following restriction: "When multiplying DW x DW, the dst > >> cannot be accumulator." > >> --- > >> src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 6 +++++- > >> 1 file changed, 5 insertions(+), 1 deletion(-) > >> > >> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp > >> index c228743..b2335bd 100644 > >> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp > >> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp > >> @@ -1069,7 +1069,11 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) > >> case nir_op_umul_high: { > >> struct brw_reg acc = retype(brw_acc_reg(8), dst.type); > >> > >> - emit(MUL(acc, op[0], op[1])); > >> + if (devinfo->gen >=8) > > > > Space after >= > > > >> + emit(MUL(acc, op[0], retype(op[1], BRW_REGISTER_TYPE_UW))); > >> + else > >> + emit(MUL(acc, op[0], op[1])); > >> + > > > > Do the tests/spec/arb_gpu_shader5/execution/built-in-functions/vs-{i,u}mulExtended*.shader_test > > tests currently fail on BDW with INTEL_DEBUG=vec4? If so, presumably > > this fixes it? It didn't fix anything > > Reviewed-by: Matt Turner <<a href="mailto:mattst88@gmail.com">mattst88@gmail.com</a>> > > Well, I'm glad you applied my R-b, but it would have been nice to fix > the typo I noted or answer the question I asked before committing the > patch. Sorry, was queuing up patches to Jenkins and push.