<html> <head> <base href="https://bugs.freedesktop.org/" /> </head> <body> <div> <a class="bz_bug_link bz_status_RESOLVED bz_closed" title="RESOLVED NOTABUG - Performance improvement : Please consider hardware ɢᴘᴜ rendering in llvmpipe" href="https://bugs.freedesktop.org/show_bug.cgi?id=93686#c28">Comment # 28</a> on <a class="bz_bug_link bz_status_RESOLVED bz_closed" title="RESOLVED NOTABUG - Performance improvement : Please consider hardware ɢᴘᴜ rendering in llvmpipe" href="https://bugs.freedesktop.org/show_bug.cgi?id=93686">bug 93686</a> from <a class="email" href="mailto:jason@jlekstrand.net" title="Jason Ekstrand <jason@jlekstrand.net>"> Jason Ekstrand</a> <pre>(In reply to ytrezq from <a href="show_bug.cgi?id=93686#c15">comment #15</a>) > (In reply to Alex Deucher from <a href="show_bug.cgi?id=93686#c13">comment #13</a>) > > I can't speak for intel, but on AMD APUs, while the GPU appears as a device > > on the PCIE bus, it actually has a much faster internal connection to the > > memory controller. > You’re still confusing things. Of course they use the same memory controller > directly. Of course they share the same memory modules. > However they can’t read or write in memory of each others. So this behave > like an external card ᴘᴄɪe card with it’s own memory modules (if we forget > the bandwidth is also shared with an another device so each ones slow each > others). > > So if you want to send or receive data it can only happens over the ᴘᴄɪe > bus, triggering the same synchronisations problems of external chipsets due > to the bus bandwidth and instructions overhead. > > Unified memory will only happen in future generations of graphics cards, but > only behind a ᴘᴄɪe bus (which will slow things because there’s still the > memory controller bus adding overhead), so we’re far from the time were ɢᴘᴜs > of ᴀᴘᴜs will be able to access ʀᴀᴍ of ᴄᴘᴜs with the same overhead (at that > time it’s expected ʀᴀᴍ modules would have been merged into the ᴄᴘᴜ chip > meaning there would be no longer separated ʀᴀᴍ modules). This is just plain false. Intel GPUs have, for a very long time shared memory with the CPU. They both have access to the exact same physical pages. The memory segregation you are referring to was a quirk of the Windows drivers of the time. The Linus driver, as far as I know, has always allowed the GPU and CPU to freely access the same memory. On big-core systems (i3, i5, i7), they even share the same L3 cache so access is coherent between the two. (In reply to ytrezq from <a href="show_bug.cgi?id=93686#c26">comment #26</a>) > Concerning synchronisation, it don’t removes shared bandwidth with the ᴄᴘᴜ > <a href="http://superuser.com/q/789816/282033">http://superuser.com/q/789816/282033</a> Please don't post links to random user focussed Q&A sites or forums to try and explain to us how our hardware works. The people you are talking to here are driver developers! We (AMD and Intel at least) have access to the real documentation and know the hardware details very well.</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the QA Contact for the bug.</li> <li>You are the assignee for the bug.</li> </ul> </body> </html>