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<body><span class="vcard"><a class="email" href="mailto:ytrezq@sdf-eu.org" title="ytrezq@sdf-eu.org">ytrezq@sdf-eu.org</a>
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<a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED NOTABUG - Performance improvement : Please consider hardware ɢᴘᴜ rendering in llvmpipe"
href="https://bugs.freedesktop.org/show_bug.cgi?id=93686">bug 93686</a>
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<th>What</th>
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<td style="text-align:right;">CC</td>
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<td>alexdeucher@gmail.com
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<b><a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED NOTABUG - Performance improvement : Please consider hardware ɢᴘᴜ rendering in llvmpipe"
href="https://bugs.freedesktop.org/show_bug.cgi?id=93686#c15">Comment # 15</a>
on <a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED NOTABUG - Performance improvement : Please consider hardware ɢᴘᴜ rendering in llvmpipe"
href="https://bugs.freedesktop.org/show_bug.cgi?id=93686">bug 93686</a>
from <span class="vcard"><a class="email" href="mailto:ytrezq@sdf-eu.org" title="ytrezq@sdf-eu.org">ytrezq@sdf-eu.org</a>
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<pre>(In reply to Alex Deucher from <a href="show_bug.cgi?id=93686#c13">comment #13</a>)
<span class="quote">> I can't speak for intel, but on AMD APUs, while the GPU appears as a device
> on the PCIE bus, it actually has a much faster internal connection to the
> memory controller.</span >
You’re still confusing things. Of course they use the same memory controller
directly. Of course they share the same memory modules.
However they can’t read or write in memory of each others. So this behave like
an external card ᴘᴄɪe card with it’s own memory modules (if we forget the
bandwidth is also shared with an another device so each ones slow each others).
So if you want to send or receive data it can only happens over the ᴘᴄɪe bus,
triggering the same synchronisations problems of external chipsets due to the
bus bandwidth and instructions overhead.
Unified memory will only happen in future generations of graphics cards, but
only behind a ᴘᴄɪe bus (which will slow things because there’s still the memory
controller bus adding overhead), so we’re far from the time were ɢᴘᴜs of ᴀᴘᴜs
will be able to access ʀᴀᴍ of ᴄᴘᴜs with the same overhead (at that time it’s
expected ʀᴀᴍ modules would have been merged into the ᴄᴘᴜ chip meaning there
would be no longer separated ʀᴀᴍ modules).</pre>
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