<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Aug 7, 2015 at 1:14 PM, Chris Wilson <span dir="ltr"><<a href="mailto:chris@chris-wilson.co.uk" target="_blank">chris@chris-wilson.co.uk</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Fixes regression from<br>
commit 8c17d53823c77ac1c56b0548e4e54f69a33285f1<br>
Author: Kenneth Graunke <<a href="mailto:kenneth@whitecape.org">kenneth@whitecape.org</a>><br>
Date: Wed Apr 15 03:04:33 2015 -0700<br>
<br>
i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.<br>
<br>
which adjusted the coordinates to be relative to the nearest cacheline.<br>
However, this then offsets the coordinates by up to 63 and this may then<br>
cause them to overflow the BLT limits. For the well aligned large<br>
transfer case, we can use 32bpp pixels and so reduce the coordinates by<br>
4 (versus the current 8bpp pixels). We also have to be more careful<br>
doing the last line just in case it may exceed the coordinate limit.<br>
<br>
Bugzilla: <a href="https://bugs.freedesktop.org/show_bug.cgi?id=90734" rel="noreferrer" target="_blank">https://bugs.freedesktop.org/show_bug.cgi?id=90734</a><br>
Signed-off-by: Chris Wilson <<a href="mailto:chris@chris-wilson.co.uk">chris@chris-wilson.co.uk</a>><br>
Cc: Kenneth Graunke <<a href="mailto:kenneth@whitecape.org">kenneth@whitecape.org</a>><br>
Cc: Ian Romanick <<a href="mailto:ian.d.romanick@intel.com">ian.d.romanick@intel.com</a>><br>
Cc: Anuj Phogat <<a href="mailto:anuj.phogat@gmail.com">anuj.phogat@gmail.com</a>><br>
Cc: <a href="mailto:mesa-stable@lists.freedesktop.org">mesa-stable@lists.freedesktop.org</a><br>
---<br>
src/mesa/drivers/dri/i965/intel_blit.c | 72 ++++++++++++++++------------------<br>
1 file changed, 34 insertions(+), 38 deletions(-)<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c<br>
index 4d1defc..845fcde 100644<br>
--- a/src/mesa/drivers/dri/i965/intel_blit.c<br>
+++ b/src/mesa/drivers/dri/i965/intel_blit.c<br>
@@ -765,47 +765,43 @@ intel_emit_linear_blit(struct brw_context *brw,<br>
int16_t src_x, dst_x;<br>
bool ok;<br>
<br>
- /* The pitch given to the GPU must be DWORD aligned, and<br>
- * we want width to match pitch. Max width is (1 << 15 - 1),<br>
- * rounding that down to the nearest DWORD is 1 << 15 - 4<br>
- */<br>
- pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 1), 4);<br>
- height = (pitch == 0) ? 1 : size / pitch;<br>
- src_x = src_offset % 64;<br>
- dst_x = dst_offset % 64;<br>
- ok = intelEmitCopyBlit(brw, 1,<br>
- pitch, src_bo, src_offset - src_x, I915_TILING_NONE,<br>
- INTEL_MIPTREE_TRMODE_NONE,<br>
- pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE,<br>
- INTEL_MIPTREE_TRMODE_NONE,<br>
- src_x, 0, /* src x/y */<br>
- dst_x, 0, /* dst x/y */<br>
- pitch, height, /* w, h */<br>
- GL_COPY);<br>
- if (!ok)<br>
- _mesa_problem(ctx, "Failed to linear blit %dx%d\n", pitch, height);<br>
-<br>
- src_offset += pitch * height;<br>
- dst_offset += pitch * height;<br>
- src_x = src_offset % 64;<br>
- dst_x = dst_offset % 64;<br>
- size -= pitch * height;<br>
- assert (size < (1 << 15));<br>
- pitch = ALIGN(size, 4);<br>
-<br>
- if (size != 0) {<br>
+ do {<br>
+ /* The pitch given to the GPU must be DWORD aligned, and<br>
+ * we want width to match pitch. Max width is (1 << 15 - 1),<br>
+ * rounding that down to the nearest DWORD is 1 << 15 - 4<br>
+ */<br>
+ pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 64), 4);<br>
+ height = (size < pitch || pitch == 0) ? 1 : size / pitch;<br>
+<br>
+ src_x = src_offset % 64;<br>
+ dst_x = dst_offset % 64;<br>
+ pitch = ALIGN(MIN2(size, (1 << 15) - 64), 4);<br>
+ assert(src_x + pitch < 1 << 15);<br>
+ assert(dst_x + pitch < 1 << 15);<br>
+<br>
ok = intelEmitCopyBlit(brw, 1,<br>
- pitch, src_bo, src_offset - src_x, I915_TILING_NONE,<br>
+ pitch, src_bo, src_offset - src_x, I915_TILING_NONE,<br>
INTEL_MIPTREE_TRMODE_NONE,<br>
- pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE,<br>
+ pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE,<br>
INTEL_MIPTREE_TRMODE_NONE,<br>
- src_x, 0, /* src x/y */<br>
- dst_x, 0, /* dst x/y */<br>
- size, 1, /* w, h */<br>
- GL_COPY);<br>
- if (!ok)<br>
- _mesa_problem(ctx, "Failed to linear blit %dx%d\n", size, 1);<br>
- }<br>
+ src_x, 0, /* src x/y */<br>
+ dst_x, 0, /* dst x/y */<br>
+ MIN2(size, pitch), height, /* w, h */<br>
+ GL_COPY);<br>
+ if (!ok) {<br>
+ _mesa_problem(ctx, "Failed to linear blit %dx%d\n",<br>
+ MIN2(size, pitch), height);<br>
+ return;<br>
+ }<br>
+<br>
+ pitch *= height;<br>
+ if (size <= pitch)<br>
+ return;<br>
+<br>
+ src_offset += pitch;<br>
+ dst_offset += pitch;<br>
+ size -= pitch;<br>
+ } while (1);<br>
}<br>
<br>
/**<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.5.0<br>
<br>
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</font></span></blockquote></div><br></div><div class="gmail_extra">I don't see any new changes as compared to the original patch you sent</div><div class="gmail_extra">earlier.</div><div class="gmail_extra"><br></div><div class="gmail_extra">Reviewed-by: Anuj Phogat <<a href="mailto:anuj.phogat@gmail.com">anuj.phogat@gmail.com</a>></div></div>