[Nouveau] [PATCH 3/8] core: add falcon library functions
Alexandre Courbot
acourbot at nvidia.com
Tue Dec 6 05:35:40 UTC 2016
Falcon processors are used in various places of GPU chips. Although there
exist different versions of the falcon, and some variants exist, the
base set of actions performed on them is the same, which results in lots
of duplicated code.
This patch consolidates the current nvkm_falcon structure and extends it
with the following features:
* Ability for an engine to obtain and later release a given falcon,
* Abstractions for basic operations (IMEM/DMEM access, start, etc)
* Abstractions for secure operations if a falcon is secure
Abstractions make it easy to e.g. start a falcon, without having to care
about its details. For instance, falcons in secure mode need to be
started by writing to a different register.
Right now the abstractions variants only cover secure vs. non-secure
falcon, but more will come as e.g. SEC2 support is added.
This is still a WIP as other functions previously done by
engine/falcon.c need to be reimplemented. However this first step allows
to keep things simple and to discuss basic design.
Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
---
drm/nouveau/include/nvkm/core/device.h | 3 +-
drm/nouveau/include/nvkm/engine/falcon.h | 77 +++++++-
drm/nouveau/nvkm/Kbuild | 1 +-
drm/nouveau/nvkm/engine/device/base.c | 5 +-
drm/nouveau/nvkm/falcon/Kbuild | 2 +-
drm/nouveau/nvkm/falcon/base.c | 259 ++++++++++++++++++++++++-
drm/nouveau/nvkm/falcon/falcon_v1.c | 212 ++++++++++++++++++++-
drm/nouveau/nvkm/falcon/priv.h | 31 +++-
8 files changed, 590 insertions(+), 0 deletions(-)
create mode 100644 drm/nouveau/nvkm/falcon/Kbuild
create mode 100644 drm/nouveau/nvkm/falcon/base.c
create mode 100644 drm/nouveau/nvkm/falcon/falcon_v1.c
create mode 100644 drm/nouveau/nvkm/falcon/priv.h
diff --git a/drm/nouveau/include/nvkm/core/device.h b/drm/nouveau/include/nvkm/core/device.h
index d426b86e2712..3751a8991b9b 100644
--- a/drm/nouveau/include/nvkm/core/device.h
+++ b/drm/nouveau/include/nvkm/core/device.h
@@ -116,6 +116,9 @@ struct nvkm_device {
struct notifier_block nb;
} acpi;
+ struct mutex falcon_mutex;
+ struct list_head falcons;
+
struct nvkm_bar *bar;
struct nvkm_bios *bios;
struct nvkm_bus *bus;
diff --git a/drm/nouveau/include/nvkm/engine/falcon.h b/drm/nouveau/include/nvkm/engine/falcon.h
index e6baf039c269..cfbef43586cd 100644
--- a/drm/nouveau/include/nvkm/engine/falcon.h
+++ b/drm/nouveau/include/nvkm/engine/falcon.h
@@ -4,13 +4,39 @@
#include <core/engine.h>
struct nvkm_fifo_chan;
+enum nvkm_falconidx {
+ NVKM_FALCON_PMU = 0,
+ NVKM_FALCON_RESERVED = 1,
+ NVKM_FALCON_FECS = 2,
+ NVKM_FALCON_GPCCS = 3,
+ NVKM_FALCON_NVDEC = 4,
+ NVKM_FALCON_SEC2 = 7,
+ NVKM_FALCON_END = 11,
+ NVKM_FALCON_INVALID = 0xffffffff,
+};
+
+enum nvkm_falcon_dmaidx {
+ FALCON_DMAIDX_UCODE = 0,
+ FALCON_DMAIDX_VIRT = 1,
+ FALCON_DMAIDX_PHYS_VID = 2,
+ FALCON_DMAIDX_PHYS_SYS_COH = 3,
+ FALCON_DMAIDX_PHYS_SYS_NCOH = 4,
+};
+
+extern const char *nvkm_falcon_name[];
+
struct nvkm_falcon {
const struct nvkm_falcon_func *func;
+ const struct nvkm_subdev *subdev;
struct nvkm_engine engine;
+ enum nvkm_devidx devidx;
+ enum nvkm_falconidx id;
+ struct list_head head;
u32 addr;
u8 version;
u8 secret;
+ bool debug;
struct nvkm_memory *core;
bool external;
@@ -19,12 +45,14 @@ struct nvkm_falcon {
u32 limit;
u32 *data;
u32 size;
+ u8 ports;
} code;
struct {
u32 limit;
u32 *data;
u32 size;
+ u8 ports;
} data;
};
@@ -42,6 +70,55 @@ struct nvkm_falcon_func {
} data;
void (*init)(struct nvkm_falcon *);
void (*intr)(struct nvkm_falcon *, struct nvkm_fifo_chan *);
+ void (*load_imem)(struct nvkm_falcon *, void *, u32, u32, u16, u8, bool);
+ void (*load_dmem)(struct nvkm_falcon *, void *, u32, u32, u8);
+ void (*read_dmem)(struct nvkm_falcon *, u32, u32, u8, void *);
+ void (*bind_context)(struct nvkm_falcon *, struct nvkm_gpuobj *);
+ int (*wait_for_halt)(struct nvkm_falcon *, u32);
+ void (*set_start_addr)(struct nvkm_falcon *, u32 start_addr);
+ void (*start)(struct nvkm_falcon *);
+ int (*enable)(struct nvkm_falcon *falcon);
+ void (*disable)(struct nvkm_falcon *falcon);
+
struct nvkm_sclass sclass[];
};
+
+struct nvkm_falcon *nvkm_falcon_get(const struct nvkm_subdev *,
+ enum nvkm_falconidx);
+void nvkm_falcon_put(struct nvkm_falcon *falcon);
+
+static inline u32
+nvkm_falcon_rd32(struct nvkm_falcon *falcon, u32 addr)
+{
+ return nvkm_rd32(falcon->subdev->device, falcon->addr + addr);
+}
+
+static inline void
+nvkm_falcon_wr32(struct nvkm_falcon *falcon, u32 addr, u32 data)
+{
+ nvkm_wr32(falcon->subdev->device, falcon->addr + addr, data);
+}
+
+static inline u32
+nvkm_falcon_mask(struct nvkm_falcon *falcon, u32 addr, u32 mask, u32 val)
+{
+ struct nvkm_device *device = falcon->subdev->device;
+
+ return nvkm_mask(device, falcon->addr + addr, mask, val);
+}
+
+void nvkm_falcon_load_imem(struct nvkm_falcon *, void *, u32, u32, u16, u8,
+ bool);
+void nvkm_falcon_load_dmem(struct nvkm_falcon *, void *, u32, u32, u8);
+void nvkm_falcon_read_dmem(struct nvkm_falcon *, u32, u32, u8, void *);
+void nvkm_falcon_bind_context(struct nvkm_falcon *, struct nvkm_gpuobj *);
+void nvkm_falcon_set_start_addr(struct nvkm_falcon *, u32);
+void nvkm_falcon_start(struct nvkm_falcon *);
+int nvkm_falcon_wait_for_halt(struct nvkm_falcon *, u32);
+int nvkm_falcon_enable(struct nvkm_falcon *);
+void nvkm_falcon_disable(struct nvkm_falcon *);
+int nvkm_falcon_reset(struct nvkm_falcon *);
+
+void nvkm_falcon_cleanup(struct nvkm_device *);
+
#endif
diff --git a/drm/nouveau/nvkm/Kbuild b/drm/nouveau/nvkm/Kbuild
index 2832147b676c..e664378f6eda 100644
--- a/drm/nouveau/nvkm/Kbuild
+++ b/drm/nouveau/nvkm/Kbuild
@@ -1,3 +1,4 @@
include $(src)/nvkm/core/Kbuild
+include $(src)/nvkm/falcon/Kbuild
include $(src)/nvkm/subdev/Kbuild
include $(src)/nvkm/engine/Kbuild
diff --git a/drm/nouveau/nvkm/engine/device/base.c b/drm/nouveau/nvkm/engine/device/base.c
index 2cbcffe78c3e..683ffcf0eaa4 100644
--- a/drm/nouveau/nvkm/engine/device/base.c
+++ b/drm/nouveau/nvkm/engine/device/base.c
@@ -2496,6 +2496,9 @@ nvkm_device_del(struct nvkm_device **pdevice)
if (device->func->dtor)
*pdevice = device->func->dtor(device);
+
+ nvkm_falcon_cleanup(device);
+
mutex_unlock(&nv_devices_mutex);
kfree(*pdevice);
@@ -2715,6 +2718,8 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
}
mutex_init(&device->mutex);
+ mutex_init(&device->falcon_mutex);
+ INIT_LIST_HEAD(&device->falcons);
for (i = 0; i < NVKM_SUBDEV_NR; i++) {
#define _(s,m) case s: \
diff --git a/drm/nouveau/nvkm/falcon/Kbuild b/drm/nouveau/nvkm/falcon/Kbuild
new file mode 100644
index 000000000000..be9d41ad73bf
--- /dev/null
+++ b/drm/nouveau/nvkm/falcon/Kbuild
@@ -0,0 +1,2 @@
+nvkm-y += nvkm/falcon/base.o
+nvkm-y += nvkm/falcon/falcon_v1.o
diff --git a/drm/nouveau/nvkm/falcon/base.c b/drm/nouveau/nvkm/falcon/base.c
new file mode 100644
index 000000000000..efef9fc63407
--- /dev/null
+++ b/drm/nouveau/nvkm/falcon/base.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "priv.h"
+
+#include <subdev/mc.h>
+
+const char *
+nvkm_falcon_name[] = {
+ [NVKM_FALCON_PMU] = "PMU",
+ [NVKM_FALCON_RESERVED] = "<reserved>",
+ [NVKM_FALCON_FECS] = "FECS",
+ [NVKM_FALCON_GPCCS] = "GPCCS",
+ [NVKM_FALCON_NVDEC] = "NVDEC",
+ [NVKM_FALCON_SEC2] = "SEC2",
+ [NVKM_FALCON_END] = "<invalid>",
+};
+
+static const struct {
+ enum nvkm_devidx devidx;
+ u32 addr;
+} falcon_props[] = {
+ [NVKM_FALCON_PMU] = { NVKM_SUBDEV_PMU, 0x10a000 },
+ [NVKM_FALCON_FECS] = { NVKM_ENGINE_GR, 0x409000 },
+ [NVKM_FALCON_GPCCS] = { NVKM_ENGINE_GR, 0x41a000 },
+ [NVKM_FALCON_NVDEC] = { NVKM_ENGINE_NVDEC, 0x84000 },
+ [NVKM_FALCON_SEC2] = { NVKM_ENGINE_SEC, 0x87000 },
+ [NVKM_FALCON_END] = { NVKM_SUBDEV_NR, 0x0 },
+};
+
+static struct nvkm_falcon *
+nvkm_falcon_find(const struct nvkm_subdev *subdev, enum nvkm_falconidx id)
+{
+ struct nvkm_device *device = subdev->device;
+ struct nvkm_falcon *falcon;
+
+ list_for_each_entry(falcon, &device->falcons, head) {
+ if (falcon->id == id)
+ return falcon;
+ }
+
+ return NULL;
+}
+
+struct nvkm_falcon *
+nvkm_falcon_get(const struct nvkm_subdev *subdev, enum nvkm_falconidx id)
+{
+ struct nvkm_device *device = subdev->device;
+ struct nvkm_falcon *falcon;
+
+ if (falcon_props[id].addr == 0x0)
+ return ERR_PTR(-EINVAL);
+
+ mutex_lock(&device->falcon_mutex);
+
+ falcon = nvkm_falcon_find(subdev, id);
+
+ /* Create the falcon structure if using it for the first time */
+ if (!falcon) {
+ u32 reg;
+
+ falcon = kzalloc(sizeof(*falcon), GFP_KERNEL);
+ if (!falcon) {
+ mutex_unlock(&device->falcon_mutex);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ INIT_LIST_HEAD(&falcon->head);
+ falcon->id = id;
+ falcon->addr = falcon_props[id].addr;
+ falcon->devidx = falcon_props[id].devidx;
+
+ /* Get falcon version and characteristics */
+ reg = nvkm_rd32(device, falcon->addr + 0x12c);
+ falcon->version = reg & 0xf;
+ falcon->secret = (reg >> 4) & 0x3;
+ falcon->code.ports = (reg >> 8) & 0xf;
+ falcon->data.ports = (reg >> 12) & 0xf;
+
+ reg = nvkm_rd32(device, falcon->addr + 0x108);
+ falcon->code.limit = (reg & 0x1ff) << 8;
+ falcon->data.limit = (reg & 0x3fe00) >> 1;
+
+ reg = nvkm_rd32(device, falcon->addr + 0xc08);
+ falcon->debug = (reg >> 20) & 0x1;
+
+ if (falcon->secret == 0)
+ falcon->func = &nvkm_falcon_v1_func;
+ else
+ falcon->func = &nvkm_falcon_v1_secure_func;
+
+ list_add(&falcon->head, &device->falcons);
+ } else if (falcon->subdev) {
+ nvkm_error(subdev, "%s falcon already acquired by %s!\n",
+ nvkm_falcon_name[id],
+ nvkm_subdev_name[falcon->subdev->index]);
+ mutex_unlock(&device->falcon_mutex);
+ return ERR_PTR(-EAGAIN);
+ }
+
+ falcon->subdev = subdev;
+
+ mutex_unlock(&device->falcon_mutex);
+
+ nvkm_debug(subdev, "acquired %s falcon\n", nvkm_falcon_name[id]);
+
+ return falcon;
+}
+
+void
+nvkm_falcon_put(struct nvkm_falcon *falcon)
+{
+ const struct nvkm_subdev *subdev = falcon->subdev;
+ struct nvkm_device *device = subdev->device;
+ enum nvkm_falconidx id = falcon->id;
+
+ mutex_lock(&device->falcon_mutex);
+
+ if (!falcon->subdev)
+ nvkm_warn(subdev, "trying to release non-acquired falcon %s\n",
+ nvkm_falcon_name[id]);
+ else
+ nvkm_debug(subdev, "released %s falcon\n",
+ nvkm_falcon_name[id]);
+
+ falcon->subdev = NULL;
+
+ mutex_unlock(&device->falcon_mutex);
+}
+
+void
+nvkm_falcon_cleanup(struct nvkm_device *device)
+{
+ struct nvkm_falcon *falcon, *n;
+
+ list_for_each_entry_safe(falcon, n, &device->falcons, head) {
+ if (falcon->subdev)
+ nvdev_warn(device,
+ "falcon %s still held by %s at exit time\n",
+ nvkm_falcon_name[falcon->id],
+ nvkm_subdev_name[falcon->subdev->index]);
+ list_del(&falcon->head);
+ kfree(falcon);
+ }
+}
+
+void
+nvkm_falcon_load_imem(struct nvkm_falcon *falcon, void *data, u32 start,
+ u32 size, u16 tag, u8 port, bool secure)
+{
+ if (secure && !falcon->secret) {
+ nvkm_warn(falcon->subdev,
+ "writing with secure tag on a non-secure falcon!\n");
+ return;
+ }
+
+ falcon->func->load_imem(falcon, data, start, size, tag, port,
+ secure);
+}
+
+void
+nvkm_falcon_load_dmem(struct nvkm_falcon *falcon, void *data, u32 start,
+ u32 size, u8 port)
+{
+ falcon->func->load_dmem(falcon, data, start, size, port);
+}
+
+void
+nvkm_falcon_read_dmem(struct nvkm_falcon *falcon, u32 start, u32 size, u8 port,
+ void *data)
+{
+ falcon->func->read_dmem(falcon, start, size, port, data);
+}
+
+void
+nvkm_falcon_bind_context(struct nvkm_falcon *falcon, struct nvkm_gpuobj *inst)
+{
+ if (!falcon->func->bind_context) {
+ nvkm_error(falcon->subdev,
+ "Context binding not supported on this falcon!\n");
+ return;
+ }
+
+ falcon->func->bind_context(falcon, inst);
+}
+
+void
+nvkm_falcon_set_start_addr(struct nvkm_falcon *falcon, u32 start_addr)
+{
+ falcon->func->set_start_addr(falcon, start_addr);
+}
+
+void
+nvkm_falcon_start(struct nvkm_falcon *falcon)
+{
+ falcon->func->start(falcon);
+}
+
+int
+nvkm_falcon_enable(struct nvkm_falcon *falcon)
+{
+ struct nvkm_device *device = falcon->subdev->device;
+ int ret;
+
+ nvkm_mc_enable(device, falcon->devidx);
+ ret = falcon->func->enable(falcon);
+ if (ret) {
+ nvkm_mc_disable(device, falcon->devidx);
+ return ret;
+ }
+
+ return 0;
+}
+
+void
+nvkm_falcon_disable(struct nvkm_falcon *falcon)
+{
+ struct nvkm_device *device = falcon->subdev->device;
+
+ /* already disabled, return or wait_idle will timeout */
+ if (!nvkm_mc_enabled(device, falcon->devidx))
+ return;
+
+ falcon->func->disable(falcon);
+
+ nvkm_mc_disable(device, falcon->devidx);
+}
+
+int
+nvkm_falcon_reset(struct nvkm_falcon *falcon)
+{
+ nvkm_falcon_disable(falcon);
+ return nvkm_falcon_enable(falcon);
+}
+
+int
+nvkm_falcon_wait_for_halt(struct nvkm_falcon *falcon, u32 ms)
+{
+ return falcon->func->wait_for_halt(falcon, ms);
+}
diff --git a/drm/nouveau/nvkm/falcon/falcon_v1.c b/drm/nouveau/nvkm/falcon/falcon_v1.c
new file mode 100644
index 000000000000..25a791f0fb9a
--- /dev/null
+++ b/drm/nouveau/nvkm/falcon/falcon_v1.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "priv.h"
+#include <core/gpuobj.h>
+#include <core/memory.h>
+#include <subdev/timer.h>
+
+static void
+nvkm_falcon_v1_load_imem(struct nvkm_falcon *falcon, void *data, u32 start,
+ u32 size, u16 tag, u8 port, bool secure)
+{
+ struct nvkm_device *device = falcon->subdev->device;
+ u32 base = falcon->addr;
+ u32 reg;
+ int i;
+
+ reg = start | BIT(24) | (secure ? BIT(28) : 0);
+ nvkm_wr32(device, base + 0x180 + (port * 16), reg);
+ for (i = 0; i < size / 4; i++) {
+ /* write new tag every 256B */
+ if ((i & 0x3f) == 0) {
+ nvkm_wr32(device, base + 0x188, tag);
+ tag++;
+ }
+ nvkm_wr32(device, base + 0x184, ((u32 *)data)[i]);
+ }
+}
+
+static void
+nvkm_falcon_v1_load_dmem(struct nvkm_falcon *falcon, void *data, u32 start,
+ u32 size, u8 port)
+{
+ struct nvkm_device *device = falcon->subdev->device;
+ u32 base = falcon->addr;
+ int i;
+
+ nvkm_wr32(device, base + 0x1c0 + (port * 16), start | (0x1 << 24));
+ for (i = 0; i < size / 4; i++)
+ nvkm_wr32(device, base + 0x1c4, ((u32 *)data)[i]);
+}
+
+static void
+nvkm_falcon_v1_read_dmem(struct nvkm_falcon *falcon, u32 start, u32 size,
+ u8 port, void *data)
+{
+ struct nvkm_device *device = falcon->subdev->device;
+ u32 base = falcon->addr;
+ int i;
+
+ nvkm_wr32(device, base + 0x1c0 + (port * 16), start | (0x1 << 25));
+ for (i = 0; i < size / 4; i++)
+ ((u32 *)data)[i] = nvkm_rd32(device, base + 0x1c4);
+}
+
+static void
+nvkm_falcon_v1_bind_context(struct nvkm_falcon *falcon, struct nvkm_gpuobj *ctx)
+{
+ u32 inst_loc;
+
+ /* disable instance block binding */
+ if (ctx == NULL) {
+ nvkm_falcon_wr32(falcon, 0x10c, 0x0);
+ return;
+ }
+
+ nvkm_falcon_wr32(falcon, 0x10c, 0x1);
+
+ /* setup apertures - virtual */
+ nvkm_falcon_wr32(falcon, 0xe00 + 4 * FALCON_DMAIDX_UCODE, 0x4);
+ nvkm_falcon_wr32(falcon, 0xe00 + 4 * FALCON_DMAIDX_VIRT, 0x0);
+ /* setup apertures - physical */
+ nvkm_falcon_wr32(falcon, 0xe00 + 4 * FALCON_DMAIDX_PHYS_VID, 0x4);
+ nvkm_falcon_wr32(falcon, 0xe00 + 4 * FALCON_DMAIDX_PHYS_SYS_COH, 0x5);
+ nvkm_falcon_wr32(falcon, 0xe00 + 4 * FALCON_DMAIDX_PHYS_SYS_NCOH, 0x6);
+
+ /* Set context */
+ if (nvkm_memory_target(ctx->memory) == NVKM_MEM_TARGET_VRAM)
+ inst_loc = 0x0; /* FB */
+ else
+ inst_loc = 0x3; /* Non-coherent sysmem */
+
+ /* Enable context */
+ nvkm_falcon_mask(falcon, 0x048, 0x1, 0x1);
+ nvkm_falcon_wr32(falcon, 0x480,
+ ((ctx->addr >> 12) & 0xfffffff) |
+ (inst_loc << 28) | (1 << 30));
+}
+
+static void
+nvkm_falcon_v1_set_start_addr(struct nvkm_falcon *falcon, u32 start_addr)
+{
+ nvkm_falcon_wr32(falcon, 0x104, start_addr);
+}
+
+static void
+nvkm_falcon_v1_start(struct nvkm_falcon *falcon)
+{
+ nvkm_falcon_wr32(falcon, 0x100, 0x2);
+}
+
+static void
+nvkm_falcon_v1_secure_start(struct nvkm_falcon *falcon)
+{
+ u32 reg = nvkm_falcon_rd32(falcon, 0x100);
+
+ if (reg & BIT(6))
+ nvkm_falcon_wr32(falcon, 0x130, 0x2);
+ else
+ nvkm_falcon_wr32(falcon, 0x100, 0x2);
+}
+
+static int
+nvkm_falcon_v1_wait_for_halt(struct nvkm_falcon *falcon, u32 ms)
+{
+ struct nvkm_device *device = falcon->subdev->device;
+ int ret;
+
+ ret = nvkm_wait_msec(device, ms, falcon->addr + 0x100, 0x10, 0x10);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int
+falcon_v1_wait_idle(struct nvkm_falcon *falcon)
+{
+ struct nvkm_device *device = falcon->subdev->device;
+ int ret;
+
+ ret = nvkm_wait_msec(device, 10, falcon->addr + 0x04c, 0xffff, 0x0);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int
+nvkm_falcon_v1_enable(struct nvkm_falcon *falcon)
+{
+ struct nvkm_device *device = falcon->subdev->device;
+ int ret;
+
+ ret = nvkm_wait_msec(device, 10, falcon->addr + 0x10c, 0x6, 0x0);
+ if (ret < 0) {
+ nvkm_error(falcon->subdev, "Falcon mem scrubbing timeout\n");
+ return ret;
+ }
+
+ ret = falcon_v1_wait_idle(falcon);
+ if (ret)
+ return ret;
+
+ /* enable IRQs */
+ nvkm_falcon_wr32(falcon, 0x010, 0xff);
+
+ return 0;
+}
+
+static void
+nvkm_falcon_v1_disable(struct nvkm_falcon *falcon)
+{
+ /* disable IRQs and wait for any previous code to complete */
+ nvkm_falcon_wr32(falcon, 0x014, 0xff);
+ falcon_v1_wait_idle(falcon);
+}
+
+const struct nvkm_falcon_func
+nvkm_falcon_v1_func = {
+ .load_imem = nvkm_falcon_v1_load_imem,
+ .load_dmem = nvkm_falcon_v1_load_dmem,
+ .read_dmem = nvkm_falcon_v1_read_dmem,
+ .bind_context = nvkm_falcon_v1_bind_context,
+ .start = nvkm_falcon_v1_start,
+ .wait_for_halt = nvkm_falcon_v1_wait_for_halt,
+ .enable = nvkm_falcon_v1_enable,
+ .disable = nvkm_falcon_v1_disable,
+ .set_start_addr = nvkm_falcon_v1_set_start_addr,
+};
+
+const struct nvkm_falcon_func
+nvkm_falcon_v1_secure_func = {
+ .load_imem = nvkm_falcon_v1_load_imem,
+ .load_dmem = nvkm_falcon_v1_load_dmem,
+ .read_dmem = nvkm_falcon_v1_read_dmem,
+ .bind_context = nvkm_falcon_v1_bind_context,
+ .start = nvkm_falcon_v1_secure_start,
+ .wait_for_halt = nvkm_falcon_v1_wait_for_halt,
+ .enable = nvkm_falcon_v1_enable,
+ .disable = nvkm_falcon_v1_disable,
+ .set_start_addr = nvkm_falcon_v1_set_start_addr,
+};
diff --git a/drm/nouveau/nvkm/falcon/priv.h b/drm/nouveau/nvkm/falcon/priv.h
new file mode 100644
index 000000000000..f30729f14ad3
--- /dev/null
+++ b/drm/nouveau/nvkm/falcon/priv.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVKM_CORE_FALCON_PRIV_H
+#define __NVKM_CORE_FALCON_PRIV_H
+
+#include <engine/falcon.h>
+
+extern const struct nvkm_falcon_func nvkm_falcon_v1_func;
+extern const struct nvkm_falcon_func nvkm_falcon_v1_secure_func;
+
+#endif
--
git-series 0.8.10
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