<br><br><div class="gmail_quote">On Thu, May 27, 2010 at 23:03, Stephane Marchesin <span dir="ltr"><<a href="mailto:stephane.marchesin@gmail.com">stephane.marchesin@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">
<br><br><div class="gmail_quote"><div><div></div><div class="h5">On Thu, May 27, 2010 at 22:47, Ben Skeggs <span dir="ltr"><<a href="mailto:skeggsb@gmail.com" target="_blank">skeggsb@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div>On Thu, 2010-05-27 at 17:55 +0300, Pekka Paalanen wrote:<br>
> On Wed, 26 May 2010 23:24:57 +0200<br>
> Maarten Maathuis <<a href="mailto:madman2003@gmail.com" target="_blank">madman2003@gmail.com</a>> wrote:<br>
><br>
> > For NV04 i can understand, since it's irq driven fences, so let's<br>
> > split the question.<br>
> ><br>
> > NV10+: can we reduce it to just spin_lock?<br>
><br>
> I don't know the answer, but I know the theory: if there is<br>
> any path, that can take the spinlock from an interrupt<br>
> service path, then you must use the irq-safe version everywhere.<br>
</div>We could, the interrupt-based path is currently only used on really old<br>
chips that don't have REF_CNT.<br>
<div><br>
><br>
> > NV04: can't we rely on a normal spin lock and add it as well in<br>
> > nv04_graph_mthd_set_ref?<br>
><br>
> So if NV04 fences are driven by irqs, and the ISR needs to<br>
> take the lock, then no, you cannot revert to irq-unsafe spinlocks.<br>
> I'm not sure how it relates to ISR bottom halves, though.<br>
><br>
> Note, that also irq-unsafe spinlocks disable preemption, which<br>
> might be enough to disturb audio.<br>
</div>The spinlock was actually only ever meant to protect the list itself and<br>
not the sequence counters.<br>
<br>
I've attached a patch removing the spinlock use everywhere except when<br>
we're actually going to touch the pending list, I think<br>
last_sequence_irq is still safe as the NV04 fence IRQ handler is the<br>
only writer.<br></blockquote><div><br></div></div></div><div>That would mean the write has to be atomic everywhere though.</div><div><br></div></div></blockquote><div><br></div><div>Blah, of course the *read* has to be atomic, not the write...</div>
<div><br></div><div>Stephane</div><div><br></div></div>