<html> <head> <base href="https://bugs.freedesktop.org/" /> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - DXTn compressed normal maps produce severe artifacts on all NV5x and NVDx chipsets" href="https://bugs.freedesktop.org/show_bug.cgi?id=91551#c10">Comment # 10</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - DXTn compressed normal maps produce severe artifacts on all NV5x and NVDx chipsets" href="https://bugs.freedesktop.org/show_bug.cgi?id=91551">bug 91551</a> from <a class="email" href="mailto:imirkin@alum.mit.edu" title="Ilia Mirkin <imirkin@alum.mit.edu>"> Ilia Mirkin</a> <pre>Ah, I suspect the remaining issues are due to the fact that we're encoding things like 119: mad f32 $r75 $r4 2.000000 $r75 (8) as e000092d 04000003 add sat f32 $r11 (mul $r4 0x40000000) $r11 Which... might not be *exactly* the same thing. Unfortunately there *is* no encoding for that instruction, the nv50 emitter isn't smart enough not to emit it. Shaders with > 64 regs are sufficiently rare :( I guess we need to add a post-RA fixup to load these immediates for non-encodable instructions. Of course the question is *where* to load it... ugh. Could try to reserve a special register at RA time for it...</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the QA Contact for the bug.</li> <li>You are the assignee for the bug.</li> </ul> </body> </html>