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        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - [Patch] Preserving PCI Burst Write Wait State Select Bit"
   href="https://bugs.freedesktop.org/show_bug.cgi?id=93244">93244</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>[Patch] Preserving PCI Burst Write Wait State Select Bit
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>xorg
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>unspecified
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>x86 (IA32)
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>Linux (All)
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>enhancement
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>medium
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Driver/openchrome
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>openchrome-devel@lists.freedesktop.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>kevinbrace@gmx.com
          </td>
        </tr></table>
      <p>
        <div>
        <pre>Created <span class=""><a href="attachment.cgi?id=120329" name="attach_120329" title="[Patch] Preserving PCI Burst Write Wait State Select Bit">attachment 120329</a> <a href="attachment.cgi?id=120329&action=edit" title="[Patch] Preserving PCI Burst Write Wait State Select Bit">[details]</a></span>
[Patch] Preserving PCI Burst Write Wait State Select Bit

Preserving PCI Burst Write Wait State Select Bit.
In the process of trying to debug ACPI S3 State resume bug when an LVDS-based
DFP is used, it was discovered that OpenChrome is tinkering with PCI Burst
Write Wait State Select bit (0x3c5.0x1a[2]) on its own for no good reasons.
Typically, the option to enable 1 wait state PCI transaction in many VIA
Technologies chipset-based computers is provided in the BIOS setup, therefore,
it is prudent for OpenChrome not to tinker with this bit.
Any code references that alter this bit were removed.</pre>
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