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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - periodic audio skips with Intel HDA"
href="https://bugs.freedesktop.org/show_bug.cgi?id=49608#c51">Comment # 51</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - periodic audio skips with Intel HDA"
href="https://bugs.freedesktop.org/show_bug.cgi?id=49608">bug 49608</a>
from <span class="vcard"><a class="email" href="mailto:superquad.vortex2@gmail.com" title="Raymond <superquad.vortex2@gmail.com>"> <span class="fn">Raymond</span></a>
</span></b>
<pre><a href="https://www.google.com/patents/US20100131783">https://www.google.com/patents/US20100131783</a>
FIG. 2 illustrates an exemplary FIFO which has a FIFO size of 192 bytes, and a
threshold value of 128 bytes.
Taking 48 kHz sample rate, 2 channels each having 16 bits (or 2 bytes) for
example, each frame thus contains 4 bytes of data, wherein each frame is
regarded as a “data unit of transportation.” Whenever the amount of stream data
in the FIFO is less than 128 bytes (i.e., the threshold), the HDAC 15 will
issue a bus mater cycle. As each frame is transported in an interval time of
20.83 micro second (μs) (=1/(48×103)), which is regarded as a “time unit of
transportation,” the 128 bytes therefore can keep 32 frames (=128/4) of data
for about 666 micro second (=32×20.83) without under run.
you need to use 32bits or more channels, higher rate to get 0.5ms latency</pre>
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