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2014-9-30 下午2:45 於 "David Henningsson" <<a href="mailto:david.henningsson@canonical.com">david.henningsson@canonical.com</a>> 寫道:<br>
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> On 2014-09-29 14:49, Alexander E. Patrakov wrote:<br>
>><br>
>> 29.09.2014 18:16, David Henningsson wrote:<br>
>>><br>
>>> Ah, now I get it - the problem is not that the buffer might become half<br>
>>> empty, the problem is that you might estimate to sleep too long, so your<br>
>>> process time is effectively cut in half: if you previously had problems<br>
>>> with process times > 20 ms, you can now potentially have problems with<br>
>>> process times > 10 ms.<br>
>>><br>
>>> I doubt this is a blocker, as this will resolve itself naturally since<br>
>>> the potential underruns that might occur will just cause the process<br>
>>> time to increase, but it's a very valid point and worthy some thought in<br>
>>> case this patch will ever be v2.<br>
>>><br>
>>> (Still waiting for somebody to report back that it's actually making a<br>
>>> difference - otherwise I won't fix anything that isn't broken.)<br>
>><br>
>><br>
>> I think it is worth testing on a Xonar DX or any other card with an<br>
>> insanely large FIFO size. Unfortunately, I don't own this card, and it<br>
>> would be a rather big stretch to ask my friend (who has it) to test a<br>
>> patched version of PulseAudio :(<br>
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> I don't have any Xonar DX card either, but out of curiousity, what FIFO size, in actual numbers/latency, is it that you would call "insanely large"?<br>
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<p><a href="https://git.kernel.org/cgit/linux/kernel/git/tiwai/sound.git/commit/sound/pci/oxygen?id=4e9c58cb1219bcbcf6e698ed6541b275048bfa88">https://git.kernel.org/cgit/linux/kernel/git/tiwai/sound.git/commit/sound/pci/oxygen?id=4e9c58cb1219bcbcf6e698ed6541b275048bfa88</a></p>
<p>Take a look at patent US 8412866</p>
<p> System and method of dynamically switching queue threshold<br>
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The DMA 150 has a queue, such as a first-in first-out buffer (“FIFO”) for maintaining the stream on the HDA link 16 by storing sufficient amount of data, such that no data under run or overrun occurs. Before sending out data to the HDA link 16, the HDAC 15 will issue a bus master cycle to request next stream data from the system memory 13 whenever the amount of the stream data in the FIFO is less than a threshold value. The FIFO threshold value and the burst length are associated with the FIFO size, as shown in Table 1, where h represents a hexadecimal number, and DW represents a double word (or 4-byte data).<br>
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