xf86-video-intel: src/i965_render.c
Zhenyu Wang
zhen at kemper.freedesktop.org
Thu Mar 22 04:35:50 EET 2007
src/i965_render.c | 48 +++++++++++++++++++++++++-----------------------
1 files changed, 25 insertions(+), 23 deletions(-)
New commits:
diff-tree 20b26854abdacb6dc45cba2d81d515b2e47e25f1 (from 3025fa0fb2bf5ace7076796e45e2560fe8410e8d)
Author: Wang Zhenyu <zhenyu.z.wang at intel.com>
Date: Thu Mar 22 10:33:15 2007 +0800
EXA: don't smash vertex header in G965
Originally we smashed vertex header to store texture
coordinates, this is working as we only use sf/wm kernel
and disable all other stages on pipeline. But better to
not do this. This also cleans up vertex elements state
and makes vertex buffer order looks "normal".
diff --git a/src/i965_render.c b/src/i965_render.c
index 3cf694f..bfbb77e 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -817,7 +817,8 @@ i965_prepare_composite(int op, PicturePt
sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */
sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */
sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */
- sf_state->thread3.urb_entry_read_offset = 0;
+ /* don't smash vertex header, read start from dw8 */
+ sf_state->thread3.urb_entry_read_offset = 1;
sf_state->thread3.dispatch_grf_start_reg = 3;
sf_state->thread4.max_threads = SF_MAX_THREADS - 1;
sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
@@ -1005,37 +1006,38 @@ i965_prepare_composite(int op, PicturePt
/* Set up our vertex elements, sourced from the single vertex buffer.
*/
OUT_RING(BRW_3DSTATE_VERTEX_ELEMENTS | ((2 * nelem) - 1));
+ /* vertex coordinates */
OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
VE0_VALID |
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
(0 << VE0_OFFSET_SHIFT));
OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
- ((pMask ? BRW_VFCOMPONENT_NOSTORE: BRW_VFCOMPONENT_STORE_1_FLT)
- << VE1_VFCOMPONENT_2_SHIFT) |
- ((pMask ? BRW_VFCOMPONENT_NOSTORE: BRW_VFCOMPONENT_STORE_1_FLT)
- << VE1_VFCOMPONENT_3_SHIFT) |
- (0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
+ (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
+ /* u0, v0 */
+ OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
+ VE0_VALID |
+ (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
+ (8 << VE0_OFFSET_SHIFT)); /* offset vb in bytes */
+ OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+ (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+ (BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_2_SHIFT) |
+ (BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_3_SHIFT) |
+ (8 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
+ /* u1, v1 */
if (pMask) {
OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
VE0_VALID |
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
- (8 << VE0_OFFSET_SHIFT));
+ (16 << VE0_OFFSET_SHIFT));
OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
(BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_2_SHIFT) |
(BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_3_SHIFT) |
- (2 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
+ (10 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
}
- OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
- VE0_VALID |
- (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
- ((pMask?16:8) << VE0_OFFSET_SHIFT)); /* offset vb in bytes */
- OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
- (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
- (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
- (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
- (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
ADVANCE_LP_RING();
}
@@ -1089,34 +1091,34 @@ i965_composite(PixmapPtr pDst, int srcX,
i = 0;
/* rect (x2,y2) */
+ vb[i++] = (float)(dstX + w);
+ vb[i++] = (float)(dstY + h);
vb[i++] = src_x[2] / pI830->scale_units[0][0];
vb[i++] = src_y[2] / pI830->scale_units[0][1];
if (has_mask) {
vb[i++] = mask_x[2] / pI830->scale_units[1][0];
vb[i++] = mask_y[2] / pI830->scale_units[1][1];
}
- vb[i++] = (float)(dstX + w);
- vb[i++] = (float)(dstY + h);
/* rect (x1,y2) */
+ vb[i++] = (float)dstX;
+ vb[i++] = (float)(dstY + h);
vb[i++] = src_x[1] / pI830->scale_units[0][0];
vb[i++] = src_y[1] / pI830->scale_units[0][1];
if (has_mask) {
vb[i++] = mask_x[1] / pI830->scale_units[1][0];
vb[i++] = mask_y[1] / pI830->scale_units[1][1];
}
- vb[i++] = (float)dstX;
- vb[i++] = (float)(dstY + h);
/* rect (x1,y1) */
+ vb[i++] = (float)dstX;
+ vb[i++] = (float)dstY;
vb[i++] = src_x[0] / pI830->scale_units[0][0];
vb[i++] = src_y[0] / pI830->scale_units[0][1];
if (has_mask) {
vb[i++] = mask_x[0] / pI830->scale_units[1][0];
vb[i++] = mask_y[0] / pI830->scale_units[1][1];
}
- vb[i++] = (float)dstX;
- vb[i++] = (float)dstY;
{
BEGIN_LP_RING(6);
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