xf86-video-intel: 2 commits - src/i810_reg.h src/i830_driver.c src/i830_sdvo.c
Zhenyu Wang
zhen at kemper.freedesktop.org
Wed Jun 4 02:04:22 PDT 2008
src/i810_reg.h | 4 ++++
src/i830_driver.c | 8 ++++----
src/i830_sdvo.c | 4 +++-
3 files changed, 11 insertions(+), 5 deletions(-)
New commits:
commit beb72ae5aa053303f5cc419e9c9d7c6db964f160
Author: Hong Liu <hong.liu at intel.com>
Date: Wed Jun 4 16:58:05 2008 +0800
Set SDVO sync polarity to default on 965
Fix fd.o bug 15766
diff --git a/src/i810_reg.h b/src/i810_reg.h
index 9da258a..e0b0c27 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -1252,6 +1252,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
#define SDVOC_GANG_MODE (1 << 16)
#define SDVO_BORDER_ENABLE (1 << 7)
+/** new with 965, default is to be set */
+#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
+#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
+/** 915/945 only, read-only bit */
#define SDVOB_PCIE_CONCURRENCY (1 << 3)
#define SDVO_DETECTED (1 << 2)
/* Bits to be preserved when writing */
diff --git a/src/i830_sdvo.c b/src/i830_sdvo.c
index 2379127..331059b 100644
--- a/src/i830_sdvo.c
+++ b/src/i830_sdvo.c
@@ -873,7 +873,9 @@ i830_sdvo_mode_set(xf86OutputPtr output, DisplayModePtr mode,
/* Set the SDVO control regs. */
if (IS_I965G(pI830)) {
- sdvox = SDVO_BORDER_ENABLE;
+ sdvox = SDVO_BORDER_ENABLE |
+ SDVO_VSYNC_ACTIVE_HIGH |
+ SDVO_HSYNC_ACTIVE_HIGH;
} else {
sdvox = INREG(dev_priv->output_device);
switch (dev_priv->output_device) {
commit c7fee208fd46e143965ea173984d284e1eec2a9b
Author: Hong Liu <hong.liu at intel.com>
Date: Wed Jun 4 16:56:50 2008 +0800
Fix DSPARB change on 965G
From the spec, only 965GM and IGD_GM have 128 FIFO entries.
With DSPARB change introduced by commit bd137a, I've got PIPE B
underrun when dual-headed on G35 platform.
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 1041fe3..426b20f 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -1964,12 +1964,12 @@ SetHWOperatingState(ScrnInfoPtr pScrn)
* FIFO RAM entries equally between planes A and B.
*/
if (IS_I9XX(pI830)) {
- if (IS_I915GM(pI830) || IS_I915G(pI830))
- OUTREG(DSPARB, (95 << DSPARB_CSTART_SHIFT) |
- (48 << DSPARB_BSTART_SHIFT));
- else
+ if (IS_I965GM(pI830) || IS_IGD_GM(pI830))
OUTREG(DSPARB, (127 << DSPARB_CSTART_SHIFT) |
(64 << DSPARB_BSTART_SHIFT));
+ else
+ OUTREG(DSPARB, (95 << DSPARB_CSTART_SHIFT) |
+ (48 << DSPARB_BSTART_SHIFT));
} else {
OUTREG(DSPARB, 254 << DSPARB_BEND_SHIFT | 128 << DSPARB_AEND_SHIFT);
}
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