xf86-video-intel: 3 commits - src/intel_driver.h src/intel_module.c src/sna/brw src/sna/gen6_render.c
Chris Wilson
ickle at kemper.freedesktop.org
Tue Aug 7 03:40:33 PDT 2012
src/intel_driver.h | 37 +++++++++++++++++++++++
src/intel_module.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++
src/sna/brw/brw_disasm.c | 11 ++++---
src/sna/gen6_render.c | 3 +
4 files changed, 119 insertions(+), 5 deletions(-)
New commits:
commit 5f5a10ef04a8c01b22da2284583851d84273dc2a
Author: Paulo Zanoni <paulo.r.zanoni at intel.com>
Date: Mon Aug 6 18:48:09 2012 -0300
Add Haswell PCI IDs
Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/intel_driver.h b/src/intel_driver.h
index 882d889..ac02cc7 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -192,6 +192,43 @@
#define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a
#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a
+#define PCI_CHIP_HASWELL_D_GT1 0x0402
+#define PCI_CHIP_HASWELL_D_GT2 0x0412
+#define PCI_CHIP_HASWELL_D_GT2_PLUS 0x0422
+#define PCI_CHIP_HASWELL_M_GT1 0x0406
+#define PCI_CHIP_HASWELL_M_GT2 0x0416
+#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
+#define PCI_CHIP_HASWELL_S_GT1 0x040A
+#define PCI_CHIP_HASWELL_S_GT2 0x041A
+#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A
+#define PCI_CHIP_HASWELL_SDV_D_GT1 0x0C02
+#define PCI_CHIP_HASWELL_SDV_D_GT2 0x0C12
+#define PCI_CHIP_HASWELL_SDV_D_GT2_PLUS 0x0C22
+#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06
+#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
+#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
+#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A
+#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
+#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
+#define PCI_CHIP_HASWELL_ULT_D_GT1 0x0A02
+#define PCI_CHIP_HASWELL_ULT_D_GT2 0x0A12
+#define PCI_CHIP_HASWELL_ULT_D_GT2_PLUS 0x0A22
+#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06
+#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
+#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
+#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A
+#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
+#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
+#define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D12
+#define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D22
+#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS 0x0D32
+#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16
+#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26
+#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
+#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A
+#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A
+#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
+
#endif
#define I85X_CAPID 0x44
diff --git a/src/intel_module.c b/src/intel_module.c
index ae19f75..c0403ca 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -149,6 +149,42 @@ static const SymTabRec _intel_chipsets[] = {
{PCI_CHIP_IVYBRIDGE_D_GT2, "Ivybridge Desktop (GT2)" },
{PCI_CHIP_IVYBRIDGE_S_GT1, "Ivybridge Server" },
{PCI_CHIP_IVYBRIDGE_S_GT2, "Ivybridge Server (GT2)" },
+ {PCI_CHIP_HASWELL_D_GT1, "Haswell Desktop (GT1)" },
+ {PCI_CHIP_HASWELL_D_GT2, "Haswell Desktop (GT2)" },
+ {PCI_CHIP_HASWELL_D_GT2_PLUS, "Haswell Desktop (GT2+)" },
+ {PCI_CHIP_HASWELL_M_GT1, "Haswell Mobile (GT1)" },
+ {PCI_CHIP_HASWELL_M_GT2, "Haswell Mobile (GT2)" },
+ {PCI_CHIP_HASWELL_M_GT2_PLUS, "Haswell Mobile (GT2+)" },
+ {PCI_CHIP_HASWELL_S_GT1, "Haswell Server (GT1)" },
+ {PCI_CHIP_HASWELL_S_GT2, "Haswell Server (GT2)" },
+ {PCI_CHIP_HASWELL_S_GT2_PLUS, "Haswell Server (GT2+)" },
+ {PCI_CHIP_HASWELL_SDV_D_GT1, "Haswell SDV Desktop (GT1)" },
+ {PCI_CHIP_HASWELL_SDV_D_GT2, "Haswell SDV Desktop (GT2)" },
+ {PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, "Haswell SDV Desktop (GT2+)" },
+ {PCI_CHIP_HASWELL_SDV_M_GT1, "Haswell SDV Mobile (GT1)" },
+ {PCI_CHIP_HASWELL_SDV_M_GT2, "Haswell SDV Mobile (GT2)" },
+ {PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, "Haswell SDV Mobile (GT2+)" },
+ {PCI_CHIP_HASWELL_SDV_S_GT1, "Haswell SDV Server (GT1)" },
+ {PCI_CHIP_HASWELL_SDV_S_GT2, "Haswell SDV Server (GT2)" },
+ {PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, "Haswell SDV Server (GT2+)" },
+ {PCI_CHIP_HASWELL_ULT_D_GT1, "Haswell ULT Desktop (GT1)" },
+ {PCI_CHIP_HASWELL_ULT_D_GT2, "Haswell ULT Desktop (GT2)" },
+ {PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, "Haswell ULT Desktop (GT2+)" },
+ {PCI_CHIP_HASWELL_ULT_M_GT1, "Haswell ULT Mobile (GT1)" },
+ {PCI_CHIP_HASWELL_ULT_M_GT2, "Haswell ULT Mobile (GT2)" },
+ {PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, "Haswell ULT Mobile (GT2+)" },
+ {PCI_CHIP_HASWELL_ULT_S_GT1, "Haswell ULT Server (GT1)" },
+ {PCI_CHIP_HASWELL_ULT_S_GT2, "Haswell ULT Server (GT2)" },
+ {PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, "Haswell ULT Server (GT2+)" },
+ {PCI_CHIP_HASWELL_CRW_D_GT1, "Haswell CRW Desktop (GT1)" },
+ {PCI_CHIP_HASWELL_CRW_D_GT2, "Haswell CRW Desktop (GT2)" },
+ {PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, "Haswell CRW Desktop (GT2+)" },
+ {PCI_CHIP_HASWELL_CRW_M_GT1, "Haswell CRW Mobile (GT1)" },
+ {PCI_CHIP_HASWELL_CRW_M_GT2, "Haswell CRW Mobile (GT2)" },
+ {PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, "Haswell CRW Mobile (GT2+)" },
+ {PCI_CHIP_HASWELL_CRW_S_GT1, "Haswell CRW Server (GT1)" },
+ {PCI_CHIP_HASWELL_CRW_S_GT2, "Haswell CRW Server (GT2)" },
+ {PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, "Haswell CRW Server (GT2+)" },
{-1, NULL}
};
#define NUM_CHIPSETS (sizeof(_intel_chipsets) / sizeof(_intel_chipsets[0]))
@@ -221,6 +257,43 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT1, &intel_ivybridge_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT2, &intel_ivybridge_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, &intel_haswell_info ),
+
INTEL_DEVICE_MATCH (PCI_MATCH_ANY, &intel_generic_info ),
{ 0, 0, 0 },
};
commit d8f7f933bc2d30e529730521d5628c10df0361de
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Sun Aug 5 17:18:54 2012 +0100
sna: Format markup to suppress compiler warning
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/brw/brw_disasm.c b/src/sna/brw/brw_disasm.c
index 106eed3..e6da174 100644
--- a/src/sna/brw/brw_disasm.c
+++ b/src/sna/brw/brw_disasm.c
@@ -415,6 +415,9 @@ static int string(FILE *file, const char *str)
return 0;
}
+#if defined(__GNUC__) && (__GNUC__ > 2)
+__attribute__((format(printf, 2, 3)))
+#endif
static int format(FILE *f, const char *fmt, ...)
{
char buf[1024];
@@ -833,10 +836,10 @@ void brw_disasm(FILE *file, const struct brw_instruction *inst, int gen)
int space = 0;
format(file, "%08x %08x %08x %08x\n",
- ((uint32_t*)inst)[0],
- ((uint32_t*)inst)[1],
- ((uint32_t*)inst)[2],
- ((uint32_t*)inst)[3]);
+ ((const uint32_t*)inst)[0],
+ ((const uint32_t*)inst)[1],
+ ((const uint32_t*)inst)[2],
+ ((const uint32_t*)inst)[3]);
if (inst->header.predicate_control) {
string(file, "(");
commit 4d0a259988f67f5c569c5d8000c010a7b662efd3
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Sat Aug 4 15:54:19 2012 +0100
sna/gen6: Compile fix for DBG
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/gen6_render.c b/src/sna/gen6_render.c
index 1d51300..6d4d79e 100644
--- a/src/sna/gen6_render.c
+++ b/src/sna/gen6_render.c
@@ -3284,7 +3284,8 @@ gen6_render_copy_boxes(struct sna *sna, uint8_t alu,
DBG(("%s (%d, %d)->(%d, %d) x %d, alu=%x, self-copy=%d, overlaps? %d\n",
__FUNCTION__, src_dx, src_dy, dst_dx, dst_dy, n, alu,
src_bo == dst_bo,
- overlaps(src_bo, src_dx, src_dy,
+ overlaps(sna,
+ src_bo, src_dx, src_dy,
dst_bo, dst_dx, dst_dy,
box, n, &extents)));
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