xf86-video-intel: 2 commits - src/sna/gen4_render.c src/sna/sna_accel.c
Chris Wilson
ickle at kemper.freedesktop.org
Fri Oct 19 07:05:07 PDT 2012
src/sna/gen4_render.c | 27 +++++++++++++++++----------
src/sna/sna_accel.c | 28 +++++++++++++++-------------
2 files changed, 32 insertions(+), 23 deletions(-)
New commits:
commit 299232bdb69c8c2b6231905e0f45e9cfe74fe09a
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Fri Oct 19 15:02:00 2012 +0100
sna: Reorder final checks for using the BO and setting the damage pointer
When we return NULL from sna_drawable_use_bo(), the expectation is that
the damage pointer is also NULL. However, one SHM path leaked.
References: https://bugs.freedesktop.org/show_bug.cgi?id=56180
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
index a8a0c93..593eb42 100644
--- a/src/sna/sna_accel.c
+++ b/src/sna/sna_accel.c
@@ -2791,6 +2791,7 @@ done:
DBG(("%s: using GPU bo with damage? %d\n",
__FUNCTION__, *damage != NULL));
+ assert(damage == NULL || !DAMAGE_IS_ALL(*damage));
assert(priv->gpu_bo->proxy == NULL);
assert(priv->clear == false);
assert(priv->cpu == false);
@@ -2859,6 +2860,19 @@ use_cpu_bo:
return NULL;
}
+ if (priv->shm) {
+ assert(!priv->flush);
+ sna_add_flush_pixmap(sna, priv, priv->cpu_bo);
+
+ /* As we may have flushed and retired,, recheck for busy bo */
+ if ((flags & FORCE_GPU) == 0 && !kgem_bo_is_busy(priv->cpu_bo))
+ return NULL;
+ }
+ if (priv->flush) {
+ assert(!priv->shm);
+ sna_add_flush_pixmap(sna, priv, priv->gpu_bo);
+ }
+
if (sna_damage_is_all(&priv->cpu_damage,
pixmap->drawable.width,
pixmap->drawable.height)) {
@@ -2873,21 +2887,9 @@ use_cpu_bo:
*damage = &priv->cpu_damage;
}
- if (priv->shm) {
- assert(!priv->flush);
- sna_add_flush_pixmap(sna, priv, priv->cpu_bo);
-
- /* As we may have flushed and retired,, recheck for busy bo */
- if ((flags & FORCE_GPU) == 0 && !kgem_bo_is_busy(priv->cpu_bo))
- return NULL;
- }
- if (priv->flush) {
- assert(!priv->shm);
- sna_add_flush_pixmap(sna, priv, priv->gpu_bo);
- }
-
DBG(("%s: using CPU bo with damage? %d\n",
__FUNCTION__, *damage != NULL));
+ assert(damage == NULL || !DAMAGE_IS_ALL(*damage));
assert(priv->clear == false);
return priv->cpu_bo;
}
commit 257abfdabe39629fb458ed65fab11283f7518dc4
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Wed Oct 17 23:34:22 2012 +0100
sna/gen4: Presume we need a flush upon state change similar to gen5+
References: https://bugs.freedesktop.org/show_bug.cgi?id=55627
References: https://bugs.freedesktop.org/show_bug.cgi?id=55500
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/gen4_render.c b/src/sna/gen4_render.c
index ceef528..8dc25d5 100644
--- a/src/sna/gen4_render.c
+++ b/src/sna/gen4_render.c
@@ -190,7 +190,7 @@ static const struct blendinfo {
#define SAMPLER_OFFSET(sf, se, mf, me, k) \
((((((sf) * EXTEND_COUNT + (se)) * FILTER_COUNT + (mf)) * EXTEND_COUNT + (me)) * KERNEL_COUNT + (k)) * 64)
-static void
+static bool
gen4_emit_pipelined_pointers(struct sna *sna,
const struct sna_composite_op *op,
int blend, int kernel);
@@ -243,6 +243,7 @@ static void gen4_magic_ca_pass(struct sna *sna,
gen4_emit_pipelined_pointers(sna, op, PictOpAdd,
gen4_choose_composite_kernel(PictOpAdd,
true, true, op->is_affine));
+ OUT_BATCH(MI_FLUSH);
OUT_BATCH(GEN4_3DPRIMITIVE |
GEN4_3DPRIMITIVE_VERTEX_SEQUENTIAL |
@@ -1222,11 +1223,11 @@ gen4_align_vertex(struct sna *sna, const struct sna_composite_op *op)
}
}
-static void
+static bool
gen4_emit_binding_table(struct sna *sna, uint16_t offset)
{
if (sna->render_state.gen4.surface_table == offset)
- return;
+ return false;
sna->render_state.gen4.surface_table = offset;
@@ -1238,9 +1239,11 @@ gen4_emit_binding_table(struct sna *sna, uint16_t offset)
OUT_BATCH(0); /* sf */
/* Only the PS uses the binding table */
OUT_BATCH(offset*4);
+
+ return true;
}
-static void
+static bool
gen4_emit_pipelined_pointers(struct sna *sna,
const struct sna_composite_op *op,
int blend, int kernel)
@@ -1263,7 +1266,7 @@ gen4_emit_pipelined_pointers(struct sna *sna,
key = sp | bp << 16;
if (key == sna->render_state.gen4.last_pipelined_pointers)
- return;
+ return true;
OUT_BATCH(GEN4_3DSTATE_PIPELINED_POINTERS | 5);
OUT_BATCH(sna->render_state.gen4.vs);
@@ -1275,6 +1278,7 @@ gen4_emit_pipelined_pointers(struct sna *sna,
sna->render_state.gen4.last_pipelined_pointers = key;
gen4_emit_urb(sna);
+ return false;
}
static void
@@ -1376,18 +1380,21 @@ gen4_emit_state(struct sna *sna,
const struct sna_composite_op *op,
uint16_t wm_binding_table)
{
+ bool flush = false;
+
if (FLUSH_EVERY_VERTEX)
OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH);
gen4_emit_drawing_rectangle(sna, op);
- gen4_emit_binding_table(sna, wm_binding_table);
- gen4_emit_pipelined_pointers(sna, op, op->op, op->u.gen4.wm_kernel);
+ flush |= gen4_emit_binding_table(sna, wm_binding_table);
+ flush |= gen4_emit_pipelined_pointers(sna, op, op->op, op->u.gen4.wm_kernel);
gen4_emit_vertex_elements(sna, op);
- if (kgem_bo_is_dirty(op->src.bo) || kgem_bo_is_dirty(op->mask.bo)) {
- DBG(("%s: flushing dirty (%d, %d)\n", __FUNCTION__,
+ if (flush || kgem_bo_is_dirty(op->src.bo) || kgem_bo_is_dirty(op->mask.bo)) {
+ DBG(("%s: flushing dirty (%d, %d), forced? %d\n", __FUNCTION__,
kgem_bo_is_dirty(op->src.bo),
- kgem_bo_is_dirty(op->mask.bo)));
+ kgem_bo_is_dirty(op->mask.bo),
+ flush));
OUT_BATCH(MI_FLUSH);
kgem_clear_dirty(&sna->kgem);
kgem_bo_mark_dirty(op->dst.bo);
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