xf86-video-intel: 2 commits - src/intel_module.c src/sna/gen6_render.c src/sna/gen7_render.c
Chris Wilson
ickle at kemper.freedesktop.org
Wed Jun 5 15:36:56 PDT 2013
src/intel_module.c | 28 ++++++++++++++--------------
src/sna/gen6_render.c | 5 ++++-
src/sna/gen7_render.c | 38 +++++++++++++++++++++++---------------
3 files changed, 41 insertions(+), 30 deletions(-)
New commits:
commit 70fa080d02bff9742523cea52c875d9447a78bfd
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Wed Jun 5 23:32:01 2013 +0100
sna: Include the GT details in the backend name for a chipset
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/gen6_render.c b/src/sna/gen6_render.c
index c25ef94..187cc15 100644
--- a/src/sna/gen6_render.c
+++ b/src/sna/gen6_render.c
@@ -68,6 +68,7 @@
#define GEN6_MAX_SIZE 8192
struct gt_info {
+ const char *name;
int max_vs_threads;
int max_gs_threads;
int max_wm_threads;
@@ -79,6 +80,7 @@ struct gt_info {
};
static const struct gt_info gt1_info = {
+ .name = "Sandybridge (gen6, gt1)",
.max_vs_threads = 24,
.max_gs_threads = 21,
.max_wm_threads = 40,
@@ -86,6 +88,7 @@ static const struct gt_info gt1_info = {
};
static const struct gt_info gt2_info = {
+ .name = "Sandybridge (gen6, gt2)",
.max_vs_threads = 60,
.max_gs_threads = 60,
.max_wm_threads = 80,
@@ -3704,5 +3707,5 @@ const char *gen6_render_init(struct sna *sna, const char *backend)
sna->render.max_3d_size = GEN6_MAX_SIZE;
sna->render.max_3d_pitch = 1 << 18;
- return "Sandybridge (gen6)";
+ return sna->render_state.gen6.info->name;
}
diff --git a/src/sna/gen7_render.c b/src/sna/gen7_render.c
index 6dbf1d2..3e3da48 100644
--- a/src/sna/gen7_render.c
+++ b/src/sna/gen7_render.c
@@ -75,6 +75,7 @@
#define is_aligned(x, y) (((x) & ((y) - 1)) == 0)
struct gt_info {
+ const char *name;
uint32_t max_vs_threads;
uint32_t max_gs_threads;
uint32_t max_wm_threads;
@@ -86,6 +87,7 @@ struct gt_info {
};
static const struct gt_info ivb_gt_info = {
+ .name = "Ivybridge (gen7)",
.max_vs_threads = 16,
.max_gs_threads = 16,
.max_wm_threads = (16-1) << IVB_PS_MAX_THREADS_SHIFT,
@@ -93,6 +95,7 @@ static const struct gt_info ivb_gt_info = {
};
static const struct gt_info ivb_gt1_info = {
+ .name = "Ivybridge (gen7, gt1)",
.max_vs_threads = 36,
.max_gs_threads = 36,
.max_wm_threads = (48-1) << IVB_PS_MAX_THREADS_SHIFT,
@@ -100,13 +103,23 @@ static const struct gt_info ivb_gt1_info = {
};
static const struct gt_info ivb_gt2_info = {
+ .name = "Ivybridge (gen7, gt2)",
.max_vs_threads = 128,
.max_gs_threads = 128,
.max_wm_threads = (172-1) << IVB_PS_MAX_THREADS_SHIFT,
.urb = { 256, 704, 320 },
};
+static const struct gt_info vlv_gt_info = {
+ .name = "Valleyview (gen7)",
+ .max_vs_threads = 16,
+ .max_gs_threads = 16,
+ .max_wm_threads = (16-1) << IVB_PS_MAX_THREADS_SHIFT,
+ .urb = { 128, 64, 64 },
+};
+
static const struct gt_info hsw_gt_info = {
+ .name = "Haswell (gen7.5)",
.max_vs_threads = 8,
.max_gs_threads = 8,
.max_wm_threads =
@@ -116,6 +129,7 @@ static const struct gt_info hsw_gt_info = {
};
static const struct gt_info hsw_gt1_info = {
+ .name = "Haswell (gen7.5, gt1)",
.max_vs_threads = 70,
.max_gs_threads = 70,
.max_wm_threads =
@@ -125,6 +139,7 @@ static const struct gt_info hsw_gt1_info = {
};
static const struct gt_info hsw_gt2_info = {
+ .name = "Haswell (gen7.5, gt2)",
.max_vs_threads = 140,
.max_gs_threads = 140,
.max_wm_threads =
@@ -3718,13 +3733,12 @@ static bool is_mobile(struct sna *sna)
return (DEVICE_ID(sna->PciInfo) & 0xf) == 0x6;
}
-static const char *gen7_render_setup(struct sna *sna)
+static bool gen7_render_setup(struct sna *sna)
{
struct gen7_render_state *state = &sna->render_state.gen7;
struct sna_static_stream general;
struct gen7_sampler_state *ss;
int i, j, k, l, m;
- const char *backend;
if (sna->kgem.gen == 070) {
state->info = &ivb_gt_info;
@@ -3733,10 +3747,8 @@ static const char *gen7_render_setup(struct sna *sna)
if (is_gt2(sna))
state->info = &ivb_gt2_info; /* XXX requires GT_MODE WiZ disabled */
}
- backend = "Ivybridge (gen7)";
} else if (sna->kgem.gen == 071) {
- state->info = &ivb_gt_info;
- backend = "Valleyview (gen7)";
+ state->info = &vlv_gt_info;
} else if (sna->kgem.gen == 075) {
state->info = &hsw_gt_info;
if (DEVICE_ID(sna->PciInfo) & 0xf) {
@@ -3744,9 +3756,8 @@ static const char *gen7_render_setup(struct sna *sna)
if (is_gt2(sna))
state->info = &hsw_gt2_info;
}
- backend = "Haswell (gen7.5)";
} else
- return NULL;
+ return false;
sna_static_stream_init(&general);
@@ -3807,16 +3818,13 @@ static const char *gen7_render_setup(struct sna *sna)
state->cc_blend = gen7_composite_create_blend_state(&general);
state->general_bo = sna_static_stream_fini(sna, &general);
- return state->general_bo ? backend : NULL;
+ return state->general_bo != NULL;
}
-const char *gen7_render_init(struct sna *sna, const char *parent)
+const char *gen7_render_init(struct sna *sna, const char *backend)
{
- const char *backend;
-
- backend = gen7_render_setup(sna);
- if (backend == NULL)
- return parent;
+ if (!gen7_render_setup(sna))
+ return backend;
sna->kgem.context_switch = gen7_render_context_switch;
sna->kgem.retire = gen7_render_retire;
@@ -3860,5 +3868,5 @@ const char *gen7_render_init(struct sna *sna, const char *parent)
sna->render.max_3d_size = GEN7_MAX_SIZE;
sna->render.max_3d_pitch = 1 << 18;
- return backend;
+ return sna->render_state.gen7.info->name;
}
commit 45c09bfe58c37bbf7965af25bdd4fa5c37c0908f
Author: Rodrigo Vivi <rodrigo.vivi at gmail.com>
Date: Wed Jun 5 13:07:13 2013 -0300
Add more correct names for Haswell.
As we find out more of the final product names for Haswell chipsets, we
need to update the user visible identification strings.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
diff --git a/src/intel_module.c b/src/intel_module.c
index 8b3b196..c1d0e09 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -160,19 +160,19 @@ static const SymTabRec intel_chipsets[] = {
{PCI_CHIP_IVYBRIDGE_D_GT2, "Ivybridge Desktop (GT2)" },
{PCI_CHIP_IVYBRIDGE_S_GT1, "Ivybridge Server" },
{PCI_CHIP_IVYBRIDGE_S_GT2, "Ivybridge Server (GT2)" },
- {PCI_CHIP_HASWELL_D_GT1, "Haswell Desktop (GT1)" },
- {PCI_CHIP_HASWELL_D_GT2, "Haswell Desktop (GT2)" },
+ {PCI_CHIP_HASWELL_D_GT1, "HD Graphics" },
+ {PCI_CHIP_HASWELL_D_GT2, "HD Graphics 4600" },
{PCI_CHIP_HASWELL_D_GT3, "Haswell Desktop (GT3)" },
- {PCI_CHIP_HASWELL_M_GT1, "Haswell Mobile (GT1)" },
- {PCI_CHIP_HASWELL_M_GT2, "Haswell Mobile (GT2)" },
+ {PCI_CHIP_HASWELL_M_GT1, "HD Graphics" },
+ {PCI_CHIP_HASWELL_M_GT2, "HD Graphics 4600" },
{PCI_CHIP_HASWELL_M_GT3, "Haswell Mobile (GT3)" },
- {PCI_CHIP_HASWELL_S_GT1, "Haswell Server (GT1)" },
- {PCI_CHIP_HASWELL_S_GT2, "Haswell Server (GT2)" },
+ {PCI_CHIP_HASWELL_S_GT1, "HD Graphics" },
+ {PCI_CHIP_HASWELL_S_GT2, "HD Graphics P4600/P4700" },
{PCI_CHIP_HASWELL_S_GT3, "Haswell Server (GT3)" },
{PCI_CHIP_HASWELL_B_GT1, "Haswell (GT1)" },
{PCI_CHIP_HASWELL_B_GT2, "Haswell (GT2)" },
{PCI_CHIP_HASWELL_B_GT3, "Haswell (GT3)" },
- {PCI_CHIP_HASWELL_E_GT1, "Haswell (GT1)" },
+ {PCI_CHIP_HASWELL_E_GT1, "HD Graphics" },
{PCI_CHIP_HASWELL_E_GT2, "Haswell (GT2)" },
{PCI_CHIP_HASWELL_E_GT3, "Haswell (GT3)" },
{PCI_CHIP_HASWELL_SDV_D_GT1, "Haswell SDV Desktop (GT1)" },
@@ -193,23 +193,23 @@ static const SymTabRec intel_chipsets[] = {
{PCI_CHIP_HASWELL_ULT_D_GT1, "Haswell ULT Desktop (GT1)" },
{PCI_CHIP_HASWELL_ULT_D_GT2, "Haswell ULT Desktop (GT2)" },
{PCI_CHIP_HASWELL_ULT_D_GT3, "Iris(TM) Graphics 5100" },
- {PCI_CHIP_HASWELL_ULT_M_GT1, "Haswell ULT Mobile (GT1)" },
- {PCI_CHIP_HASWELL_ULT_M_GT2, "Haswell ULT Mobile (GT2)" },
- {PCI_CHIP_HASWELL_ULT_M_GT3, "Iris(TM) Graphics 5100" },
+ {PCI_CHIP_HASWELL_ULT_M_GT1, "HD Graphics" },
+ {PCI_CHIP_HASWELL_ULT_M_GT2, "HD Graphics 4400" },
+ {PCI_CHIP_HASWELL_ULT_M_GT3, "HD Graphics 5000" },
{PCI_CHIP_HASWELL_ULT_S_GT1, "Haswell ULT Server (GT1)" },
{PCI_CHIP_HASWELL_ULT_S_GT2, "Haswell ULT Server (GT2)" },
{PCI_CHIP_HASWELL_ULT_S_GT3, "Iris(TM) Graphics 5100" },
{PCI_CHIP_HASWELL_ULT_B_GT1, "Haswell ULT (GT1)" },
{PCI_CHIP_HASWELL_ULT_B_GT2, "Haswell ULT (GT2)" },
{PCI_CHIP_HASWELL_ULT_B_GT3, "Iris(TM) Graphics 5100" },
- {PCI_CHIP_HASWELL_ULT_E_GT1, "Haswell ULT (GT1)" },
- {PCI_CHIP_HASWELL_ULT_E_GT2, "Haswell ULT (GT2)" },
+ {PCI_CHIP_HASWELL_ULT_E_GT1, "HD Graphics" },
+ {PCI_CHIP_HASWELL_ULT_E_GT2, "HD Graphics 4200" },
{PCI_CHIP_HASWELL_ULT_E_GT3, "Iris(TM) Graphics 5100" },
{PCI_CHIP_HASWELL_CRW_D_GT1, "Haswell CRW Desktop (GT1)" },
- {PCI_CHIP_HASWELL_CRW_D_GT2, "Haswell CRW Desktop (GT2)" },
+ {PCI_CHIP_HASWELL_CRW_D_GT2, "HD Graphics 4600" },
{PCI_CHIP_HASWELL_CRW_D_GT3, "Iris(TM) Pro Graphics 5200" },
{PCI_CHIP_HASWELL_CRW_M_GT1, "Haswell CRW Mobile (GT1)" },
- {PCI_CHIP_HASWELL_CRW_M_GT2, "Haswell CRW Mobile (GT2)" },
+ {PCI_CHIP_HASWELL_CRW_M_GT2, "HD Graphics 4600" },
{PCI_CHIP_HASWELL_CRW_M_GT3, "Iris(TM) Pro Graphics 5200" },
{PCI_CHIP_HASWELL_CRW_S_GT1, "Haswell CRW Server (GT1)" },
{PCI_CHIP_HASWELL_CRW_S_GT2, "Haswell CRW Server (GT2)" },
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