xf86-video-intel: src/sna/gen5_render.c
Chris Wilson
ickle at kemper.freedesktop.org
Fri Oct 4 01:38:52 PDT 2013
src/sna/gen5_render.c | 4 ++++
1 file changed, 4 insertions(+)
New commits:
commit dbf98d8963b53a3c68deb1e2624d1269c8b0d97a
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Fri Oct 4 09:36:49 2013 +0100
sna/gen5: Replace pipe-control with full MI_FLUSH for required CS stall
It appears that we need top-of-pipe synchronisation for changing of
certain state, and that the gen5 pipecontrol instruction is
insufficient. So we have to fall back on the good old MI_FLUSH in order
to make sure that the GPU invalidates its state correctly.
Reported-by: Clemens Eisserer <linuxhippy at gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51422
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/gen5_render.c b/src/sna/gen5_render.c
index af14680..2bd818a 100644
--- a/src/sna/gen5_render.c
+++ b/src/sna/gen5_render.c
@@ -1019,10 +1019,14 @@ gen5_emit_vertex_elements(struct sna *sna,
inline static void
gen5_emit_pipe_flush(struct sna *sna)
{
+#if 0
OUT_BATCH(GEN5_PIPE_CONTROL | (4 - 2));
OUT_BATCH(GEN5_PIPE_CONTROL_WC_FLUSH);
OUT_BATCH(0);
OUT_BATCH(0);
+#else
+ OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH);
+#endif
}
static void
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