VGA arbitration: API proposal

[Jon Smirl]

This from Intel's PCI Express chipset documentation:

In the following sections, it is assumed that all of the compatibility
memory ranges reside on the DMI. The exception to this rule is VGA
ranges that may be mapped to PCI Express, DMI, or to the internal
graphics device (IGD). In the absence of more specific references,
cycle descriptions referencing PCI should be interpreted as the
DMI/PCI, while cycle descriptions referencing PCI Express or IGD are
related to the PCI Express bus or the internal graphics device
respectively. The (G)MCH does not remap APIC or any other memory
spaces above TOLUD (Top of Low Usable DRAM). The TOLUD register is set
to the appropriate value by BIOS.

In this case VGA cycles can go to three place:
1) IGD - on chip graphics
2) PCI Express
3) DMI - which implements PCI

Elsewhere the documentation states that there is a priority in VGA
address decoding. If IGD VGA is turned only it will get the VGA
cycles. Then only if IGD VGA is turned off can PCI Express see the
cycles. Then only if PCI Express is turned off can PCI see them.




-- 
Jon Smirl
jonsmirl at gmail.com