MTRR setting failure
aritger at nvidia.com
Mon Mar 21 07:22:15 PST 2005
On Mon, 21 Mar 2005, Adam Jackson wrote:
> On Monday 21 March 2005 06:27, Peter Karlsson wrote:
> > On Mon, 21 Mar 2005, Mike A. Harris wrote:
> > > What is really needed, is for the Linux kernel (and other OS kernels) to
> > > aquire PAT support, as the hardware feature has existed since the Pentium
> > > Pro and later, and all Athlon CPUs. Not sure about AMD K6/K5 or other
> > > brands/models. The X server should then try to use the interfaces the
> > > kernel would provide to set cacheability on page level granularity, and
> > > only try to use MTRRs if the system does not support PAT.
> > Do you mean intel's 'Performance Acceleration Technology' (a.k.a. PAT)?
> No, Page Attribute Table:
> Think MTRRs but with per-page granularity, rather than having a max of six-ish
> ranges for the whole system.
Right. And note that PAT is even more important (or, rather,
MTRRs are less useful) on PCI-E systems where you no longer have
pages nicely organized in a physically contiguous GART. MTRRs can
only operate on a physically contiguous range of pages.
A while ago, Terence Ripperda did some work to enable PAT in
the Linux kernel. Note that actually enabling and using PAT is
trivial. The interesting part is making sure you don't use PAT to
set attributes on a page that conflict with the attributes of any
other mapping of that page (cache aliasing).
The cachemap mechanism discussed here:
was work in progress towards preventing cache aliasing when using
PAT, but that work got sidetracked. If anyone is interested in
helping to wrap this up, please let me know and I can put you in
touch with Terence.
> - ajax
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