Intel i915GM with SDVO CH7021A support?

[Eric Anholt]

On Tue, 2007-01-02 at 23:19 +0000, Will . wrote:
> >Hey, good work.
> 
> Thanks for the encouragement, much appreciated.
> 
> >Yes, please post the code. If you have a chance, I think you'll find the
> >modesetting branch a lot easier to work in for this kind of thing, it
> >has SDVO communication code all set up.
> 
> I think that's good advice (which I know I should have taken). Hopefully if 
> there is time available to add support for this I'll pull the latest 
> modesetting branch and try to put my changes in the correct places. I assume 
> you'll want to minimize conditional branching etc as much as possible so if 
> someone has the time to talk to me about whats required I'll do my best to 
> contribute as appropriate.

Yeah, doing it in the modesetting branch should be much more satisfying.

Also, in the future, diff -u is greatly preferred to traditional context
diffs.

> =======================================================
> 
> //output connection (DAC select ?)
> 
> * memset(s->sdvo_regs, 0, 9);
> * s->sdvo_regs[SDVO_I2C_ARG_0] = 0x4;
> * s->sdvo_regs[SDVO_I2C_ARG_4] = 0x4;
> * s->sdvo_regs[SDVO_I2C_OPCODE] = 0x5; //SDVO_CMD_SET_ACTIVE_OUTPUTS
> 
> //Composite= 0x4 DACB
> //Component = 0x10; DACA
> //Scart  = 0x20; DACC
> 
> The ports bellow were found using an incremental scan of the first 256 op 
> codes (I used an xv hack and a shell script - probably not the best solution 
> but it worked). Perhaps a better/alternative tactic may have been to look 
> for opcodes that responded as it seems set/get pairs may travel in similar 
> or adjoining locations.
> 
> The op codes listed may alter their range and function depending on the 
> output type that is selected and possibly the tv format e.g. 
> interlace/progressive. Most seem to support clock values. I've listed my 
> notes with approximate defaults that relate to my setup, most of the notes 
> relate to the component output I was using at the time.
> 
> 93 (CONTRAST)
> 
> approx 60 is def
> 
> 96 - 0x60 (BRIGHTNESS)
> 
> approx 60 is def
> 
> 99- 0x63 (WIDTH) Height is done with input timing
> 
> approx 28 is def
> 
> 105 (HORZ POSITION)
> 
> 500 is def
> 520 is better
> 
> 507 is correct for my display using scart
> 
> 108 (VERT POSITION)
> 
> 199 is correct for my display using scart (the default)
> 
> 81 (SHARPNESS/FILTER??)
> 
> 111 (FILTER??)
> 
> 87 (COLOUR - AMOUNT)
> 
> approx 60 is def 0=BW 100=SATURATED
> 
> 90 (HUE)
> 
> approx 60 is def
> 
> 45 (UNKNOWN - Causes display to blank and sync loss)
> 
> 59 (UNKNOWN - Causes display to flash)
> 
> =======================================================
> 
> A corresponding modeline is required for the TV output to work, I think this 
> can be generated using create preferred input timings (does this take note 
> of the selected tv format). There is a relationship between input timing and 
> output timings related to the tv format selected. I didn't notice much 
> difference when playing with the sdvo output timings for this device, 
> presumably output timings are fixed by the tv format.
> 
> Modeline "720x576_SDVO"   0.96 720 763 795 864  576 585 587 630 +vsync
> 
> #original from BIOS trace
> #Modeline "720x576_SDVO"   0.96 720 756 788 864  576 616 618 700 +vsync
> 
> I made a corresponding adjustment to the 630 above in the input timings to 
> get the overscan working as desired. There were some discrepancies between 
> the original mode line from the bios trace (PAL 720x576 using 915resolution 
> and vbetool) and the dtd that was created by create input timings, not sure 
> if this is because I miss interpreted the data or due to some other reason. 
> The only discrepancy was vsync offset which seemed way off.
> 
> When adjusting the overscan I reduced m in the PLL timings to gain a sync 
> lock. I don't have the correct fixups for the PLL registers so I just used 
> guess work, there is undoubtedly a proper way to calculate this but the full 
> PLL routines may be required for them to be of any use.
> 
> e.g. I noticed the following not sure if its of any use though
> 
> 3000/96/2=15.625 (Horizontal timing for PAL)
> 
> 3000=clock value from create preferred input timings (ok  not exactly but 
> 2999+1)
> 96=the modeline clock from the BIOS trace
> 2=because its interlaced???
> 
> By adjusting the sync offset of the modeline horizontal/vertical position is 
> adjustable in the normal way, I didn't adjust the input timing for this, 
> there are sdvo op codes available for horiz/vert position anyway.
> 
> I've left sync disabled in ADPA, I think the sync is taken from 7021A's PLL 
> anyway. I seem to remembed that if sync in ADPA is enabled that the CRT 
> output will also be enabled, presumably with the TV timings from the 7021A. 
> Perhaps this could be used to get exact tv timing for DVI if that isn't 
> already possible
> 
> That's all I can remember for the moment hope this helps!

-- 
Eric Anholt                             anholt at FreeBSD.org
eric at anholt.net                         eric.anholt at intel.com
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