[PATCH] drm/amd/powerplay: Tidy up print level functions
Tom St Denis
tstdenis82 at gmail.com
Thu Aug 18 13:54:45 UTC 2016
Tidy the print_current_perforce_level() functions as well
as make the Carrizo version a bit more comparable.
Signed-off-by: Tom St Denis <tom.stdenis at amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 20 ++++++++++----------
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 13 ++++---------
drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c | 12 ++++--------
.../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 13 ++++---------
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 12 ++++--------
5 files changed, 26 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index 40153847675a..a1c070766d6a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1587,10 +1587,10 @@ cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
int result;
if (sclk_index >= NUM_SCLK_LEVELS) {
- seq_printf(m, "\n invalid sclk dpm profile %d\n", sclk_index);
+ seq_printf(m, "invalid sclk dpm profile %d\n", sclk_index);
} else {
sclk = table->entries[sclk_index].clk;
- seq_printf(m, "\n index: %u sclk: %u MHz\n", sclk_index, sclk/100);
+ seq_printf(m, "gfx.sclk = %u MHz\n", sclk/100);
}
tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
@@ -1599,26 +1599,26 @@ cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
vddgfx = cz_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp);
- seq_printf(m, "\n vddnb: %u vddgfx: %u\n", vddnb, vddgfx);
+ seq_printf(m, "gfx.vddnb = %u\ngfx.vddgfx = %u\n", vddnb, vddgfx);
- seq_printf(m, "\n uvd %sabled\n", cz_hwmgr->uvd_power_gated ? "dis" : "en");
+ seq_printf(m, "uvd.enabled = %d\n", cz_hwmgr->uvd_power_gated ? 0 : 1);
if (!cz_hwmgr->uvd_power_gated) {
if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
- seq_printf(m, "\n invalid uvd dpm level %d\n", uvd_index);
+ seq_printf(m, "invalid uvd dpm level %d\n", uvd_index);
} else {
vclk = uvd_table->entries[uvd_index].vclk;
dclk = uvd_table->entries[uvd_index].dclk;
- seq_printf(m, "\n index: %u uvd vclk: %u MHz dclk: %u MHz\n", uvd_index, vclk/100, dclk/100);
+ seq_printf(m, "uvd.index = %u\nuvd.vclk = %u MHz\nuvd.dclk = %u MHz\n", uvd_index, vclk/100, dclk/100);
}
}
- seq_printf(m, "\n vce %sabled\n", cz_hwmgr->vce_power_gated ? "dis" : "en");
+ seq_printf(m, "vce.enabled = %d\n", cz_hwmgr->vce_power_gated ? 0 : 1);
if (!cz_hwmgr->vce_power_gated) {
if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
- seq_printf(m, "\n invalid vce dpm level %d\n", vce_index);
+ seq_printf(m, "invalid vce dpm level %d\n", vce_index);
} else {
ecclk = vce_table->entries[vce_index].ecclk;
- seq_printf(m, "\n index: %u vce ecclk: %u MHz\n", vce_index, ecclk/100);
+ seq_printf(m, "vce.index = %u\nvce.ecclk = %u MHz\n", vce_index, ecclk/100);
}
}
@@ -1630,7 +1630,7 @@ cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
activity_percent = 50;
}
- seq_printf(m, "\n [GPU load]: %u %%\n\n", activity_percent);
+ seq_printf(m, "gpu.load = %u %%\n", activity_percent);
}
static void cz_hw_print_display_cfg(
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
index e93492b15c52..f8fb00c1df4b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
@@ -5082,25 +5082,20 @@ static void fiji_print_current_perforce_level(
struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
-
sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
-
mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
- seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
- mclk / 100, sclk / 100);
offset = data->soft_regs_start + offsetof(SMU73_SoftRegisters, AverageGraphicsActivity);
activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
activity_percent += 0x80;
activity_percent >>= 8;
- seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
-
- seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
-
- seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
+ seq_printf(m, "gfx.mclk = %u MHz\ngfx.sclk = %u MHz\n", mclk/100, sclk/100);
+ seq_printf(m, "uvd.enabled = %d\n", data->uvd_power_gated ? 0 : 1);
+ seq_printf(m, "vce.enabled = %d\n", data->vce_power_gated ? 0 : 1);
+ seq_printf(m, "gpu.load = %u %%\n", activity_percent > 100 ? 100 : activity_percent);
}
static int fiji_program_display_gap(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
index f48f3eac5ba4..8e1c82bf66f9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
@@ -5124,24 +5124,20 @@ iceland_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetSclkFrequency));
-
sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetMclkFrequency));
-
mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
- seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n", mclk/100, sclk/100);
offset = data->soft_regs_start + offsetof(SMU71_SoftRegisters, AverageGraphicsActivity);
activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
activity_percent += 0x80;
activity_percent >>= 8;
- seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
-
- seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
-
- seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
+ seq_printf(m, "gfx.mclk = %u MHz\ngfx.sclk = %u MHz\n", mclk/100, sclk/100);
+ seq_printf(m, "uvd.enabled = %d\n", data->uvd_power_gated ? 0 : 1);
+ seq_printf(m, "vce.enabled = %d\n", data->vce_power_gated ? 0 : 1);
+ seq_printf(m, "gpu.load = %u %%\n", activity_percent > 100 ? 100 : activity_percent);
}
int iceland_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index 23d455c6243b..61b3b84acd92 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -3979,25 +3979,20 @@ polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
-
sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
-
mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
- seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
- mclk / 100, sclk / 100);
offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
activity_percent += 0x80;
activity_percent >>= 8;
- seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
-
- seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
-
- seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
+ seq_printf(m, "gfx.mclk = %u MHz\ngfx.sclk = %u MHz\n", mclk/100, sclk/100);
+ seq_printf(m, "uvd.enabled = %d\n", data->uvd_power_gated ? 0 : 1);
+ seq_printf(m, "vce.enabled = %d\n", data->vce_power_gated ? 0 : 1);
+ seq_printf(m, "gpu.load = %u %%\n", activity_percent > 100 ? 100 : activity_percent);
}
static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
index e09847d16366..e948217a3993 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
@@ -5197,24 +5197,20 @@ tonga_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetSclkFrequency));
-
sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetMclkFrequency));
-
mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
- seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n", mclk/100, sclk/100);
offset = data->soft_regs_start + offsetof(SMU72_SoftRegisters, AverageGraphicsActivity);
activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
activity_percent += 0x80;
activity_percent >>= 8;
- seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
-
- seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
-
- seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
+ seq_printf(m, "gfx.mclk = %u MHz\ngfx.sclk = %u MHz\n", mclk/100, sclk/100);
+ seq_printf(m, "uvd.enabled = %d\n", data->uvd_power_gated ? 0 : 1);
+ seq_printf(m, "vce.enabled = %d\n", data->vce_power_gated ? 0 : 1);
+ seq_printf(m, "gpu.load = %u %%\n", activity_percent > 100 ? 100 : activity_percent);
}
static int tonga_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
--
2.9.2
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