[PATCH libdrm 1/2] amdgpu: sync amdgpu_drm.h with the kernel

[Edward O'Callaghan]

This series is,

Reviewed-by: Edward O'Callaghan <funfunctor at folklore1984.net>

On 08/20/2016 12:15 AM, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
> 
> ---
>  include/drm/amdgpu_drm.h | 42 ++++++++++++++++++++++++++----------------
>  1 file changed, 26 insertions(+), 16 deletions(-)
> 
> diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
> index 92f5970..d192052 100644
> --- a/include/drm/amdgpu_drm.h
> +++ b/include/drm/amdgpu_drm.h
> @@ -27,20 +27,24 @@
>   *    Kevin E. Martin <martin at valinux.com>
>   *    Gareth Hughes <gareth at valinux.com>
>   *    Keith Whitwell <keith at tungstengraphics.com>
>   */
>  
>  #ifndef __AMDGPU_DRM_H__
>  #define __AMDGPU_DRM_H__
>  
>  #include "drm.h"
>  
> +#if defined(__cplusplus)
> +extern "C" {
> +#endif
> +
>  #define DRM_AMDGPU_GEM_CREATE		0x00
>  #define DRM_AMDGPU_GEM_MMAP		0x01
>  #define DRM_AMDGPU_CTX			0x02
>  #define DRM_AMDGPU_BO_LIST		0x03
>  #define DRM_AMDGPU_CS			0x04
>  #define DRM_AMDGPU_INFO			0x05
>  #define DRM_AMDGPU_GEM_METADATA		0x06
>  #define DRM_AMDGPU_GEM_WAIT_IDLE	0x07
>  #define DRM_AMDGPU_GEM_VA		0x08
>  #define DRM_AMDGPU_WAIT_CS		0x09
> @@ -476,20 +480,36 @@ struct drm_amdgpu_cs_chunk_data {
>  /* Query information about device: rev id, family, etc. */
>  #define AMDGPU_INFO_DEV_INFO			0x16
>  /* visible vram usage */
>  #define AMDGPU_INFO_VIS_VRAM_USAGE		0x17
>  
>  #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT	0
>  #define AMDGPU_INFO_MMR_SE_INDEX_MASK	0xff
>  #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT	8
>  #define AMDGPU_INFO_MMR_SH_INDEX_MASK	0xff
>  
> +struct drm_amdgpu_query_fw {
> +	/** AMDGPU_INFO_FW_* */
> +	uint32_t fw_type;
> +	/**
> +	 * Index of the IP if there are more IPs of
> +	 * the same type.
> +	 */
> +	uint32_t ip_instance;
> +	/**
> +	 * Index of the engine. Whether this is used depends
> +	 * on the firmware type. (e.g. MEC, SDMA)
> +	 */
> +	uint32_t index;
> +	uint32_t _pad;
> +};
> +
>  /* Input structure for the INFO ioctl */
>  struct drm_amdgpu_info {
>  	/* Where the return value will be stored */
>  	uint64_t return_pointer;
>  	/* The size of the return value. Just like "size" in "snprintf",
>  	 * it limits how many bytes the kernel can write. */
>  	uint32_t return_size;
>  	/* The query request id. */
>  	uint32_t query;
>  
> @@ -511,35 +531,21 @@ struct drm_amdgpu_info {
>  
>  		struct {
>  			uint32_t dword_offset;
>  			/** number of registers to read */
>  			uint32_t count;
>  			uint32_t instance;
>  			/** For future use, no flags defined so far */
>  			uint32_t flags;
>  		} read_mmr_reg;
>  
> -		struct {
> -			/** AMDGPU_INFO_FW_* */
> -			uint32_t fw_type;
> -			/**
> -			 * Index of the IP if there are more IPs of
> -			 * the same type.
> -			 */
> -			uint32_t ip_instance;
> -			/**
> -			 * Index of the engine. Whether this is used depends
> -			 * on the firmware type. (e.g. MEC, SDMA)
> -			 */
> -			uint32_t index;
> -			uint32_t _pad;
> -		} query_fw;
> +		struct drm_amdgpu_query_fw query_fw;
>  	};
>  };
>  
>  struct drm_amdgpu_info_gds {
>  	/** GDS GFX partition size */
>  	uint32_t gds_gfx_partition_size;
>  	/** GDS compute partition size */
>  	uint32_t compute_partition_size;
>  	/** total GDS memory size */
>  	uint32_t gds_total_size;
> @@ -634,13 +640,17 @@ struct drm_amdgpu_info_hw_ip {
>  };
>  
>  /*
>   * Supported GPU families
>   */
>  #define AMDGPU_FAMILY_UNKNOWN			0
>  #define AMDGPU_FAMILY_SI			110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
>  #define AMDGPU_FAMILY_CI			120 /* Bonaire, Hawaii */
>  #define AMDGPU_FAMILY_KV			125 /* Kaveri, Kabini, Mullins */
>  #define AMDGPU_FAMILY_VI			130 /* Iceland, Tonga */
> -#define AMDGPU_FAMILY_CZ			135 /* Carrizo */
> +#define AMDGPU_FAMILY_CZ			135 /* Carrizo, Stoney */
> +
> +#if defined(__cplusplus)
> +}
> +#endif
>  
>  #endif
> 

-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: OpenPGP digital signature
URL: <https://lists.freedesktop.org/archives/amd-gfx/attachments/20160820/69876892/attachment.sig>