Re: 答复: [PATCH 2/2] drm/amdgpu/vce3: add support for third vce ring

[Christian König]

Reviewed-by: Christian König <christian.koenig at amd.com> as well.

Do we have any requirement to support ring 2 and 3 in the near future or 
was this set just for cleanup?

Regards,
Christian.

Am 25.08.2016 um 02:03 schrieb Qu, Jim:
> These series Reivewed-by: JimQu <Jim.Qu at amd.com>
>
> Thanks
> JimQu
>
> ________________________________________
> 发件人: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> 代表 Alex Deucher <alexdeucher at gmail.com>
> 发送时间: 2016年8月25日 6:31:34
> 收件人: amd-gfx at lists.freedesktop.org
> 抄送: Deucher, Alexander
> 主题: [PATCH 2/2] drm/amdgpu/vce3: add support for third vce ring
>
> Not of much use at the moment (we don't really use
> the second ring either), but may be useful later.
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c |  4 ++--
>   drivers/gpu/drm/amd/amdgpu/vce_v3_0.c   | 22 ++++++++++++++++++----
>   3 files changed, 21 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index b34cd93..609b406 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -108,7 +108,7 @@ extern char *amdgpu_virtual_display;
>   #define AMDGPU_MAX_RINGS                       16
>   #define AMDGPU_MAX_GFX_RINGS                   1
>   #define AMDGPU_MAX_COMPUTE_RINGS               8
> -#define AMDGPU_MAX_VCE_RINGS                   2
> +#define AMDGPU_MAX_VCE_RINGS                   3
>
>   /* max number of IP instances */
>   #define AMDGPU_MAX_SDMA_INSTANCES              2
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> index da52af2..9b71d6c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> @@ -850,8 +850,8 @@ int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout)
>          struct fence *fence = NULL;
>          long r;
>
> -       /* skip vce ring1 ib test for now, since it's not reliable */
> -       if (ring == &ring->adev->vce.ring[1])
> +       /* skip vce ring1/2 ib test for now, since it's not reliable */
> +       if (ring != &ring->adev->vce.ring[0])
>                  return 0;
>
>          r = amdgpu_vce_get_create_msg(ring, 1, NULL);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 27acd28..d734ac9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -70,8 +70,10 @@ static uint32_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
>
>          if (ring == &adev->vce.ring[0])
>                  return RREG32(mmVCE_RB_RPTR);
> -       else
> +       else if (ring == &adev->vce.ring[1])
>                  return RREG32(mmVCE_RB_RPTR2);
> +       else
> +               return RREG32(mmVCE_RB_RPTR3);
>   }
>
>   /**
> @@ -87,8 +89,10 @@ static uint32_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
>
>          if (ring == &adev->vce.ring[0])
>                  return RREG32(mmVCE_RB_WPTR);
> -       else
> +       else if (ring == &adev->vce.ring[1])
>                  return RREG32(mmVCE_RB_WPTR2);
> +       else
> +               return RREG32(mmVCE_RB_WPTR3);
>   }
>
>   /**
> @@ -104,8 +108,10 @@ static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
>
>          if (ring == &adev->vce.ring[0])
>                  WREG32(mmVCE_RB_WPTR, ring->wptr);
> -       else
> +       else if (ring == &adev->vce.ring[1])
>                  WREG32(mmVCE_RB_WPTR2, ring->wptr);
> +       else
> +               WREG32(mmVCE_RB_WPTR3, ring->wptr);
>   }
>
>   static void vce_v3_0_override_vce_clock_gating(struct amdgpu_device *adev, bool override)
> @@ -229,6 +235,13 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
>          WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
>          WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
>
> +       ring = &adev->vce.ring[2];
> +       WREG32(mmVCE_RB_RPTR3, ring->wptr);
> +       WREG32(mmVCE_RB_WPTR3, ring->wptr);
> +       WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr);
> +       WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));
> +       WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4);
> +
>          mutex_lock(&adev->grbm_idx_mutex);
>          for (idx = 0; idx < 2; ++idx) {
>                  if (adev->vce.harvest_config & (1 << idx))
> @@ -345,7 +358,7 @@ static int vce_v3_0_early_init(void *handle)
>              (AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1))
>                  return -ENOENT;
>
> -       adev->vce.num_rings = 2;
> +       adev->vce.num_rings = 3;
>
>          vce_v3_0_set_ring_funcs(adev);
>          vce_v3_0_set_irq_funcs(adev);
> @@ -671,6 +684,7 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
>          switch (entry->src_data) {
>          case 0:
>          case 1:
> +       case 2:
>                  amdgpu_fence_process(&adev->vce.ring[entry->src_data]);
>                  break;
>          default:
> --
> 2.5.5
>
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