[PATCH 08/14] drm/amdgpu: fix the tahiti specific value of DEEP_SLEEP_CLK_SEL field

[Huang Rui]

Change-Id: Ib5b6146fa712192dec120702831252d9221335bb
Signed-off-by: Huang Rui <ray.huang at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 1764c0b..90842c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -4173,7 +4173,13 @@ static void si_program_response_times(struct amdgpu_device *adev)
 static void si_program_ds_registers(struct amdgpu_device *adev)
 {
 	struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
-	u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
+	u32 tmp;
+
+	/* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
+	if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
+		tmp = 0x10;
+	else
+		tmp = 0x1;
 
 	if (eg_pi->sclk_deep_sleep) {
 		WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
-- 
2.7.4