[PATCH] drm/amdgpu: refine pg code for gfx_v8.
Deucher, Alexander
Alexander.Deucher at amd.com
Mon Dec 5 21:07:05 UTC 2016
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of Zhu, Rex
> Sent: Friday, December 02, 2016 7:25 AM
> To: Alex Deucher; StDenis, Tom
> Cc: amd-gfx list
> Subject: RE: [PATCH] drm/amdgpu: refine pg code for gfx_v8.
>
> Hi Alex, Tom,
>
> > 3. always init gfx pg.
>
> >>I don't think we want to do this. We need to be able to disable various pg
> features for debugging. Also some asics don't support gfx pg (e.g., fiji), so
> we don't want to enable it on
> >>those asics.
>
> Rex: we need to call gfx_v8_0_init_pg no matter pg enable/disable.
> And delete repeated check for pg mask.
> For example:
> > - if (!(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
> > - return 0;
> We can't disable power gate when pg_flags was set to 0.
I see your point. We just assumed the default state is disabled, but it may not be. That said, we should avoid touching this stuff on asics that do not support PG at all. We should only call init_pg() on asics which support PG in the first place. I'd suggest breaking this into 3 patches:
1. fix the save/restore list
2. fix enable_cp_power_gating
3. everything else
Alex
>
> Best Regards
> Rex
>
> -----Original Message-----
> From: Alex Deucher [mailto:alexdeucher at gmail.com]
> Sent: Thursday, December 01, 2016 11:44 PM
> To: Zhu, Rex
> Cc: amd-gfx list
> Subject: Re: [PATCH] drm/amdgpu: refine pg code for gfx_v8.
>
> On Thu, Dec 1, 2016 at 3:24 AM, Rex Zhu <Rex.Zhu at amd.com> wrote:
> > 1. bit CP_PG_DISABLE was reversed.
>
> Please split this out as a separate patch. Also, with this fixed, we should be
> able to enable the AMD_PG_SUPPORT_CP flag for CZ and ST.
>
> > 2. load RLC_SRM_INDEX_CNTL_ADDR/DATA_x pairs
> > with valid addr/data.
>
> Please split this out as a separate patch.
>
> > 3. always init gfx pg.
>
> I don't think we want to do this. We need to be able to disable various pg
> features for debugging. Also some asics don't support gfx pg (e.g., fiji), so
> we don't want to enable it on those asics.
>
> > 4. delete repeated check for pg mask.
> >
> > Change-Id: I9fcc8d1f79f5fa1803cb2625aa292188a656ae6b
> > Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 85
> > +++++++++++++++--------------------
> > 1 file changed, 37 insertions(+), 48 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > index c02ae07..fee8c2a 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > @@ -3948,8 +3948,10 @@ static int gfx_v8_0_init_save_restore_list(struct
> amdgpu_device *adev)
> > temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
> > data = mmRLC_SRM_INDEX_CNTL_DATA_0;
> > for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {
> > - amdgpu_mm_wreg(adev, temp + i, unique_indices[i] & 0x3FFFF,
> false);
> > - amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20, false);
> > + if (unique_indices[i] != 0) {
> > + amdgpu_mm_wreg(adev, temp + i, unique_indices[i] &
> 0x3FFFF, false);
> > + amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20,
> false);
> > + }
> > }
> > kfree(register_list_format);
> >
> > @@ -3965,20 +3967,16 @@ static void gfx_v8_0_init_power_gating(struct
> > amdgpu_device *adev) {
> > uint32_t data;
> >
> > - if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
> > - AMD_PG_SUPPORT_GFX_SMG |
> > - AMD_PG_SUPPORT_GFX_DMG)) {
> > - WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT,
> 0x60);
> > + WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
> >
> > - data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY,
> 0x10);
> > - data = REG_SET_FIELD(data, RLC_PG_DELAY,
> POWER_DOWN_DELAY, 0x10);
> > - data = REG_SET_FIELD(data, RLC_PG_DELAY,
> CMD_PROPAGATE_DELAY, 0x10);
> > - data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY,
> 0x10);
> > - WREG32(mmRLC_PG_DELAY, data);
> > + data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
> > + data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY,
> 0x10);
> > + data = REG_SET_FIELD(data, RLC_PG_DELAY,
> CMD_PROPAGATE_DELAY, 0x10);
> > + data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY,
> 0x10);
> > + WREG32(mmRLC_PG_DELAY, data);
> >
> > - WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
> > - WREG32_FIELD(RLC_AUTO_PG_CTRL,
> GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
> > - }
> > + WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
> > + WREG32_FIELD(RLC_AUTO_PG_CTRL,
> > + GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
> > }
> >
> > static void cz_enable_sck_slow_down_on_power_up(struct
> amdgpu_device
> > *adev, @@ -3995,41 +3993,35 @@ static void
> > cz_enable_sck_slow_down_on_power_down(struct amdgpu_device
> *adev,
> >
> > static void cz_enable_cp_power_gating(struct amdgpu_device *adev,
> > bool enable) {
> > - WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 1 : 0);
> > + WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);
> > }
> >
> > static void gfx_v8_0_init_pg(struct amdgpu_device *adev) {
> > - if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
> > - AMD_PG_SUPPORT_GFX_SMG |
> > - AMD_PG_SUPPORT_GFX_DMG |
> > - AMD_PG_SUPPORT_CP |
> > - AMD_PG_SUPPORT_GDS |
> > - AMD_PG_SUPPORT_RLC_SMU_HS)) {
> > - gfx_v8_0_init_csb(adev);
> > - gfx_v8_0_init_save_restore_list(adev);
> > - gfx_v8_0_enable_save_restore_machine(adev);
> > -
> > - if ((adev->asic_type == CHIP_CARRIZO) ||
> > - (adev->asic_type == CHIP_STONEY)) {
> > - WREG32(mmRLC_JUMP_TABLE_RESTORE, adev-
> >gfx.rlc.cp_table_gpu_addr >> 8);
> > - gfx_v8_0_init_power_gating(adev);
> > - WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev-
> >gfx.cu_info.ao_cu_mask);
> > - if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
> > - cz_enable_sck_slow_down_on_power_up(adev, true);
> > - cz_enable_sck_slow_down_on_power_down(adev, true);
> > - } else {
> > - cz_enable_sck_slow_down_on_power_up(adev, false);
> > - cz_enable_sck_slow_down_on_power_down(adev,
> false);
> > - }
> > - if (adev->pg_flags & AMD_PG_SUPPORT_CP)
> > - cz_enable_cp_power_gating(adev, true);
> > - else
> > - cz_enable_cp_power_gating(adev, false);
> > - } else if (adev->asic_type == CHIP_POLARIS11) {
> > - gfx_v8_0_init_power_gating(adev);
> > + gfx_v8_0_init_csb(adev);
> > + gfx_v8_0_init_save_restore_list(adev);
> > + gfx_v8_0_enable_save_restore_machine(adev);
> > +
> > + if ((adev->asic_type == CHIP_CARRIZO) ||
> > + (adev->asic_type == CHIP_STONEY)) {
> > + WREG32(mmRLC_JUMP_TABLE_RESTORE, adev-
> >gfx.rlc.cp_table_gpu_addr >> 8);
> > + gfx_v8_0_init_power_gating(adev);
> > + WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev-
> >gfx.cu_info.ao_cu_mask);
> > + if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
> > + cz_enable_sck_slow_down_on_power_up(adev, true);
> > + cz_enable_sck_slow_down_on_power_down(adev, true);
> > + } else {
> > + cz_enable_sck_slow_down_on_power_up(adev, false);
> > + cz_enable_sck_slow_down_on_power_down(adev,
> > + false);
> > }
> > + if (adev->pg_flags & AMD_PG_SUPPORT_CP)
> > + cz_enable_cp_power_gating(adev, true);
> > + else
> > + cz_enable_cp_power_gating(adev, false);
> > + } else if (adev->asic_type == CHIP_POLARIS11) {
> > + gfx_v8_0_init_power_gating(adev);
> > }
> > +
> > }
> >
> > static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev) @@ -5570,14
> > +5562,11 @@ static int gfx_v8_0_set_powergating_state(void *handle,
> > struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> > bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
> >
> > - if (!(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
> > - return 0;
> > -
> > switch (adev->asic_type) {
> > case CHIP_CARRIZO:
> > case CHIP_STONEY:
> > - if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)
> > - cz_update_gfx_cg_power_gating(adev, enable);
> > +
> > + cz_update_gfx_cg_power_gating(adev, enable);
> >
> > if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
> >
> > gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
> > --
> > 1.9.1
> >
> > _______________________________________________
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> > amd-gfx at lists.freedesktop.org
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