[PATCH 03/12] drm/amd/display: restyle display clock calls part 1
Harry Wentland
harry.wentland at amd.com
Tue Dec 6 18:35:29 UTC 2016
From: Dmytro Laktyushkin <Dmytro.Laktyushkin at amd.com>
Change-Id: I3e65c94ea4c59ba7bc802995ad2210eeffc552e3
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin at amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng at amd.com>
Acked-by: Harry Wentland <Harry.Wentland at amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +-
.../drm/amd/display/dc/dce100/dce100_resource.c | 2 +-
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 48 ++++------------------
.../drm/amd/display/dc/dce110/dce110_resource.c | 2 +-
.../drm/amd/display/dc/dce112/dce112_resource.c | 2 +-
.../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 2 +-
.../display/dc/gpu/dce112/display_clock_dce112.c | 1 -
.../display/dc/gpu/dce112/display_clock_dce112.h | 1 -
drivers/gpu/drm/amd/display/dc/gpu/display_clock.c | 20 ---------
drivers/gpu/drm/amd/display/dc/gpu/display_clock.h | 30 --------------
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 -
.../amd/display/include/display_clock_interface.h | 35 ++++++++++++----
12 files changed, 42 insertions(+), 107 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 424a7d4b8731..70dc70685471 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1224,7 +1224,9 @@ bool dc_pre_update_surfaces_to_target(
if (prev_disp_clk < context->bw_results.dispclk_khz) {
pplib_apply_display_requirements(core_dc, context,
&context->pp_display_cfg);
- core_dc->hwss.set_display_clock(context);
+ context->res_ctx.pool->display_clock->funcs->set_clock(
+ context->res_ctx.pool->display_clock,
+ context->bw_results.dispclk_khz * 115 / 100);
core_dc->current_context->bw_results.dispclk_khz =
context->bw_results.dispclk_khz;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 9ace6d1cca79..8f18a9403525 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -984,7 +984,7 @@ static bool construct(
dce110_resource_convert_clock_state_pp_to_dc(
static_clk_info.max_clocks_state);
- dal_display_clock_store_max_clocks_state(
+ pool->base.display_clock->funcs->store_max_clocks_state(
pool->base.display_clock, max_clocks_state);
}
{
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 1a682996b531..16ee49dba97b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -497,8 +497,8 @@ static void build_audio_output(
if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
audio_output->pll_info.dp_dto_source_clock_in_khz =
- dal_display_clock_get_dp_ref_clk_frequency(
- pipe_ctx->dis_clk);
+ pipe_ctx->dis_clk->funcs->get_dp_ref_clk_frequency(
+ pipe_ctx->dis_clk);
}
audio_output->pll_info.feed_back_divider =
@@ -788,39 +788,6 @@ void dce110_enable_accelerated_mode(struct core_dc *dc)
bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
}
-/**
- * Call display_engine_clock_dce80 to perform the Dclk programming.
- */
-void dce110_set_display_clock(struct validate_context *context)
-{
- /* Program the display engine clock.
- * Check DFS bypass mode support or not. DFSbypass feature is only when
- * BIOS GPU info table reports support. */
-
- if (/*dal_adapter_service_is_dfs_bypass_enabled()*/ false) {
- /*TODO: set_display_clock_dfs_bypass(
- hws,
- path_set,
- context->res_ctx.pool->display_clock,
- context->res_ctx.min_clocks.min_dclk_khz);*/
- } else {
- /*
- * TODO: need to either port work around from DAL2 function
- * getActualRequiredDisplayClock or program displayclock without
- * calling vbios. Currently temporily work
- * around by increasing the displclk by 15 percent
- */
- dal_display_clock_set_clock(
- context->res_ctx.pool->display_clock,
- context->bw_results.dispclk_khz * 115 / 100);
- }
-
-
- /* TODO: When changing display engine clock, DMCU WaitLoop must be
- * reconfigured in order to maintain the same delays within DMCU
- * programming sequences. */
-}
-
static uint32_t compute_pstate_blackout_duration(
struct bw_fixed blackout_duration,
const struct core_stream *stream)
@@ -1267,8 +1234,10 @@ enum dc_status dce110_apply_ctx_to_hw(
apply_min_clocks(dc, context, &clocks_state, true);
if (context->bw_results.dispclk_khz
- > dc->current_context->bw_results.dispclk_khz)
- dc->hwss.set_display_clock(context);
+ > dc->current_context->bw_results.dispclk_khz)
+ context->res_ctx.pool->display_clock->funcs->set_clock(
+ context->res_ctx.pool->display_clock,
+ context->bw_results.dispclk_khz * 115 / 100);
for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx_old =
@@ -1738,7 +1707,9 @@ static void dce110_set_bandwidth(struct core_dc *dc)
program_wm_for_pipe(dc, pipe_ctx, dc->current_context);
}
- dc->hwss.set_display_clock(dc->current_context);
+ dc->current_context->res_ctx.pool->display_clock->funcs->set_clock(
+ dc->current_context->res_ctx.pool->display_clock,
+ dc->current_context->bw_results.dispclk_khz * 115 / 100);
}
static void dce110_program_front_end_for_pipe(
@@ -1959,7 +1930,6 @@ static const struct hw_sequencer_funcs dce110_funcs = {
.enable_display_power_gating = dce110_enable_display_power_gating,
.power_down_front_end = dce110_power_down_fe,
.pipe_control_lock = dce_pipe_control_lock,
- .set_display_clock = dce110_set_display_clock,
.set_displaymarks = dce110_set_displaymarks,
.increase_watermarks_for_pipe = dce110_increase_watermarks_for_pipe,
.set_bandwidth = dce110_set_bandwidth,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index cac3dc425039..a63112b2bd36 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -1315,7 +1315,7 @@ static bool construct(
dce110_resource_convert_clock_state_pp_to_dc(
static_clk_info.max_clocks_state);
- dal_display_clock_store_max_clocks_state(
+ pool->base.display_clock->funcs->store_max_clocks_state(
pool->base.display_clock, max_clocks_state);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 4e3273c0fa91..70616019ae47 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -1315,7 +1315,7 @@ static bool construct(
dce110_resource_convert_clock_state_pp_to_dc(
static_clk_info.max_clocks_state);
- dal_display_clock_store_max_clocks_state(
+ pool->base.display_clock->funcs->store_max_clocks_state(
pool->base.display_clock, max_clocks_state);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 3b626b7883d4..dfff2bfff13d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -978,7 +978,7 @@ static bool construct(
dce80_resource_convert_clock_state_pp_to_dc(
static_clk_info.max_clocks_state);
- dal_display_clock_store_max_clocks_state(
+ pool->base.display_clock->funcs->store_max_clocks_state(
pool->base.display_clock, max_clocks_state);
}
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
index bf044260c0bb..665832b0718a 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
@@ -383,7 +383,6 @@ bool dal_display_clock_dce112_construct(
struct display_clock *dc_base = &dc112->disp_clk_base;
dc_base->ctx = ctx;
- dc_base->id = CLOCK_SOURCE_ID_DCPLL;
dc_base->min_display_clk_threshold_khz = 0;
dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID;
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
index 5ab31185d29d..47a149709d91 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
@@ -32,7 +32,6 @@ struct display_clock_dce112 {
/* Max display block clocks state*/
enum clocks_state max_clks_state;
bool use_max_disp_clk;
- uint32_t crystal_freq_khz;
uint32_t dentist_vco_freq_khz;
/* Cache the status of DFS-bypass feature*/
bool dfs_bypass_enabled;
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c b/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c
index 73d982732a67..c70c6b25892e 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c
@@ -38,13 +38,6 @@ void dal_display_clock_destroy(struct display_clock **disp_clk)
*disp_clk = NULL;
}
-void dal_display_clock_set_clock(
- struct display_clock *disp_clk,
- uint32_t requested_clock_khz)
-{
- disp_clk->funcs->set_clock(disp_clk, requested_clock_khz);
-}
-
bool dal_display_clock_get_min_clocks_state(
struct display_clock *disp_clk,
enum clocks_state *clocks_state)
@@ -80,16 +73,3 @@ bool dal_display_clock_set_min_clocks_state(
return true;
}
-uint32_t dal_display_clock_get_dp_ref_clk_frequency(
- struct display_clock *disp_clk)
-{
- return disp_clk->funcs->get_dp_ref_clk_frequency(disp_clk);
-}
-
-void dal_display_clock_store_max_clocks_state(
- struct display_clock *disp_clk,
- enum clocks_state max_clocks_state)
-{
- disp_clk->funcs->store_max_clocks_state(disp_clk, max_clocks_state);
-}
-
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h b/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h
index 4db8442e717a..68d2ab0500a6 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h
@@ -28,34 +28,4 @@
#include "include/display_clock_interface.h"
-struct display_clock_funcs {
- void (*destroy)(struct display_clock **to_destroy);
- void (*set_clock)(struct display_clock *disp_clk,
- uint32_t requested_clock_khz);
- enum clocks_state (*get_min_clocks_state)(
- struct display_clock *disp_clk);
- enum clocks_state (*get_required_clocks_state)(
- struct display_clock *disp_clk,
- struct state_dependent_clocks *req_clocks);
- bool (*set_min_clocks_state)(struct display_clock *disp_clk,
- enum clocks_state clocks_state);
- uint32_t (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk);
- void (*store_max_clocks_state)(struct display_clock *disp_clk,
- enum clocks_state max_clocks_state);
-
-};
-
-struct display_clock {
- struct dc_context *ctx;
- const struct display_clock_funcs *funcs;
- uint32_t min_display_clk_threshold_khz;
- enum clock_source_id id;
-
- enum clocks_state cur_min_clks_state;
-};
-void dal_display_clock_store_max_clocks_state(
- struct display_clock *disp_clk,
- enum clocks_state max_clocks_state);
-
-
#endif /* __DAL_DISPLAY_CLOCK_H__*/
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 35a556dd9054..50d499cc01a4 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -132,8 +132,6 @@ struct hw_sequencer_funcs {
struct pipe_ctx *pipe_ctx,
struct validate_context *context);
- void (*set_display_clock)(struct validate_context *context);
-
void (*set_bandwidth)(struct core_dc *dc);
void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
diff --git a/drivers/gpu/drm/amd/display/include/display_clock_interface.h b/drivers/gpu/drm/amd/display/include/display_clock_interface.h
index ef519a284e0f..f49253714b1e 100644
--- a/drivers/gpu/drm/amd/display/include/display_clock_interface.h
+++ b/drivers/gpu/drm/amd/display/include/display_clock_interface.h
@@ -56,7 +56,31 @@ struct state_dependent_clocks {
uint32_t pixel_clk_khz;
};
-struct display_clock;
+struct display_clock {
+ struct dc_context *ctx;
+ const struct display_clock_funcs *funcs;
+ uint32_t min_display_clk_threshold_khz;
+ enum clock_source_id id;
+
+ enum clocks_state cur_min_clks_state;
+};
+
+struct display_clock_funcs {
+ void (*destroy)(struct display_clock **to_destroy);
+ void (*set_clock)(struct display_clock *disp_clk,
+ uint32_t requested_clock_khz);
+ enum clocks_state (*get_min_clocks_state)(
+ struct display_clock *disp_clk);
+ enum clocks_state (*get_required_clocks_state)(
+ struct display_clock *disp_clk,
+ struct state_dependent_clocks *req_clocks);
+ bool (*set_min_clocks_state)(struct display_clock *disp_clk,
+ enum clocks_state clocks_state);
+ uint32_t (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk);
+ void (*store_max_clocks_state)(struct display_clock *disp_clk,
+ enum clocks_state max_clocks_state);
+
+};
struct display_clock *dal_display_clock_dce112_create(
struct dc_context *ctx);
@@ -68,9 +92,7 @@ struct display_clock *dal_display_clock_dce80_create(
struct dc_context *ctx);
void dal_display_clock_destroy(struct display_clock **to_destroy);
-void dal_display_clock_set_clock(
- struct display_clock *disp_clk,
- uint32_t requested_clock_khz);
+
bool dal_display_clock_get_min_clocks_state(
struct display_clock *disp_clk,
enum clocks_state *clocks_state);
@@ -81,10 +103,5 @@ bool dal_display_clock_get_required_clocks_state(
bool dal_display_clock_set_min_clocks_state(
struct display_clock *disp_clk,
enum clocks_state clocks_state);
-uint32_t dal_display_clock_get_dp_ref_clk_frequency(
- struct display_clock *disp_clk);
-void dal_display_clock_store_max_clocks_state(
- struct display_clock *disp_clk,
- enum clocks_state max_clocks_state);
#endif /* __DISPLAY_CLOCK_INTERFACE_H__ */
--
2.9.3
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