[PATCH] drm/amdgpu/dce6: Set MASTER_UPDATE_MODE to 0 in resume_mc_access as well

[Alex Deucher]

On Tue, Dec 6, 2016 at 4:33 AM, Michel Dänzer <michel at daenzer.net> wrote:
> From: Michel Dänzer <michel.daenzer at amd.com>
>
> Looks like this was missed when dce_v6_0.c was added.
>
> Fixes: e2cdf640cbb5 ("drm/amdgpu: add display controller implementation for si v10")
> Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>

Applied.  thanks!

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index 03c8529a8e02..c81ae9c4e4b8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -456,9 +456,8 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
>         for (i = 0; i < adev->mode_info.num_crtc; i++) {
>                 if (save->crtc_enabled[i]) {
>                         tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
> -                       if ((tmp & 0x7) != 3) {
> +                       if ((tmp & 0x7) != 0) {
>                                 tmp &= ~0x7;
> -                               tmp |= 0x3;
>                                 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
>                         }
>                         tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
> --
> 2.11.0
>
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