[PATCH 2/2] drm/amdgpu: update pitcairn golden setting

[Cui, Flora]

Yes. I'm working on this.

Regards,
Flora


-----Original Message-----
From: Zhang, Jerry 
Sent: Thursday, December 15, 2016 2:43 PM
To: Cui, Flora <Flora.Cui at amd.com>; amd-gfx at lists.freedesktop.org
Cc: Cui, Flora <Flora.Cui at amd.com>
Subject: RE: [PATCH 2/2] drm/amdgpu: update pitcairn golden setting

Hi Flora,

> @@ -1206,6 +1212,7 @@ static int si_common_early_init(void *handle)
>  			AMD_CG_SUPPORT_HDP_LS |
>  			AMD_CG_SUPPORT_HDP_MGCG;
>  		adev->pg_flags = 0;
> +		adev->external_rev_id = adev->rev_id + 20;
>  		break;
It may be better to move into another patch regardless of golden setting.

BTW, it looks only VERDE has rev_id offset now. 
Do we need to add the offset for other chips about SI?

Regards,
Jerry (Junwei Zhang)

SRDC SW Development
AMD Shanghai
_____________________________________


> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf 
> Of Flora Cui
> Sent: Thursday, December 15, 2016 13:51
> To: amd-gfx at lists.freedesktop.org
> Cc: Cui, Flora
> Subject: [PATCH 2/2] drm/amdgpu: update pitcairn golden setting
> 
> Change-Id: Ie52b73ac3618174b71a1dfb5e0f152705f72c616
> Signed-off-by: Flora Cui <Flora.Cui at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/si.c | 27 +++++++++++++++++----------
>  1 file changed, 17 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c 
> b/drivers/gpu/drm/amd/amdgpu/si.c index 2439875..cf8a0a1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
> @@ -99,6 +99,7 @@ static const u32 tahiti_golden_rlc_registers[] =
> 
>  static const u32 pitcairn_golden_registers[] =  {
> +	0x17bc, 0x00000030, 0x00000011,
>  	0x2684, 0x00010000, 0x00018208,
>  	0x260c, 0xffffffff, 0x00000000,
>  	0x260d, 0xf00fffff, 0x00000400,
> @@ -116,7 +117,7 @@ static const u32 pitcairn_golden_registers[] =
>  	0x22c4, 0x0000ff0f, 0x00000000,
>  	0xa293, 0x07ffffff, 0x4e000000,
>  	0xa0d4, 0x3f3f3fff, 0x2a00126a,
> -	0x000c, 0x000000ff, 0x0040,
> +	0x000c, 0xffffffff, 0x0040,
>  	0x000d, 0x00000040, 0x00004040,
>  	0x2440, 0x07ffffff, 0x03000000,
>  	0x2418, 0x0000007f, 0x00000020,
> @@ -125,11 +126,16 @@ static const u32 pitcairn_golden_registers[] =
>  	0x2b04, 0xffffffff, 0x00000000,
>  	0x2b03, 0xffffffff, 0x32761054,
>  	0x2235, 0x0000001f, 0x00000010,
> -	0x0570, 0x000c0fc0, 0x000c0400
> +	0x0570, 0x000c0fc0, 0x000c0400,
> +	0x052c, 0x0fffffff, 0xffffffff,
> +	0x052d, 0x0fffffff, 0x0fffffff,
> +	0x052e, 0x0fffffff, 0x0fffffff,
> +	0x052f, 0x0fffffff, 0x0fffffff
>  };
> 
>  static const u32 pitcairn_golden_rlc_registers[] =  {
> +	0x263e, 0xffffffff, 0x12011003,
>  	0x3109, 0xffffffff, 0x00601004,
>  	0x311f, 0xffffffff, 0x10102020,
>  	0x3122, 0xffffffff, 0x01000020,
> @@ -618,16 +624,16 @@ static const u32 pitcairn_mgcg_cgcg_init[] =
>  	0x21c2, 0xffffffff, 0x00900100,
>  	0x311e, 0xffffffff, 0x00000080,
>  	0x3101, 0xffffffff, 0x0020003f,
> -	0xc, 0xffffffff, 0x0000001c,
> -	0xd, 0x000f0000, 0x000f0000,
> -	0x583, 0xffffffff, 0x00000100,
> -	0x409, 0xffffffff, 0x00000100,
> -	0x40b, 0x00000101, 0x00000000,
> -	0x82a, 0xffffffff, 0x00000104,
> +	0x000c, 0xffffffff, 0x0000001c,
> +	0x000d, 0x000f0000, 0x000f0000,
> +	0x0583, 0xffffffff, 0x00000100,
> +	0x0409, 0xffffffff, 0x00000100,
> +	0x040b, 0x00000101, 0x00000000,
> +	0x082a, 0xffffffff, 0x00000104,
>  	0x1579, 0xff000fff, 0x00000100,
>  	0x157a, 0x00000001, 0x00000001,
> -	0xbd4, 0x00000001, 0x00000001,
> -	0xc33, 0xc0000fff, 0x00000104,
> +	0x0bd4, 0x00000001, 0x00000001,
> +	0x0c33, 0xc0000fff, 0x00000104,
>  	0x3079, 0x00000001, 0x00000001,
>  	0x3430, 0xfffffff0, 0x00000100,
>  	0x3630, 0xfffffff0, 0x00000100
> @@ -1206,6 +1212,7 @@ static int si_common_early_init(void *handle)
>  			AMD_CG_SUPPORT_HDP_LS |
>  			AMD_CG_SUPPORT_HDP_MGCG;
>  		adev->pg_flags = 0;
> +		adev->external_rev_id = adev->rev_id + 20;
>  		break;
> 
>  	case CHIP_VERDE:
> --
> 2.7.4
> 
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