[PATCH 15/23] drm/amdgpu/mxgpu: implement register access function with KIQ

[Alex Deucher]

On Sat, Dec 17, 2016 at 11:16 AM, Xiangliang Yu <Xiangliang.Yu at amd.com> wrote:
> One of important role of KIQ is provide one way to access VF
> registers. This patch implement the feature and export interfaces.
>
> Signed-off-by: Monk Liu <Monk.Liu at amd.com>
> Signed-off-by: Xiangliang Yu <Xiangliang.Yu at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h |   4 ++
>  drivers/gpu/drm/amd/mxgpu/mxgpu_kiq.c    | 110 +++++++++++++++++++++++++++++++
>  2 files changed, 114 insertions(+)
>  create mode 100644 drivers/gpu/drm/amd/mxgpu/mxgpu_kiq.c
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> index 97aae31..c78435d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> @@ -75,4 +75,8 @@ void amdgpu_gfx_ring_emit_meta_data(struct amdgpu_ring *ring,
>  /* get full gpu access */
>  int amdgpu_get_gpu(struct amdgpu_device *adev);
>  int amdgpu_put_gpu(struct amdgpu_device *adev);
> +
> +/* access vf registers */
> +uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
> +void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
>  #endif
> diff --git a/drivers/gpu/drm/amd/mxgpu/mxgpu_kiq.c b/drivers/gpu/drm/amd/mxgpu/mxgpu_kiq.c
> new file mode 100644
> index 0000000..6e1b8e3
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/mxgpu/mxgpu_kiq.c
> @@ -0,0 +1,110 @@
> +/*
> + * Copyright 2016 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors: Xiangliang.Yu at amd.com
> + *         Monk.Liu at amd.com
> + */
> +#include "amd_mxgpu.h"
> +#include "vid.h"
> +#include "gca/gfx_8_0_d.h"
> +#include "gca/gfx_8_0_sh_mask.h"
> +
> +static void xgpu_kiq_ring_emit_rreg(struct amdgpu_ring *ring, u32 idx)
> +{
> +       struct amdgpu_device *adev = ring->adev;
> +       struct amd_xgpu *xgpu = (struct amd_xgpu *)adev->priv_data;
> +
> +       amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
> +       amdgpu_ring_write(ring, 0 |     /* src: register*/
> +                               (5 << 8) |      /* dst: memory */
> +                               (1 << 20));     /* write confirm */
> +       amdgpu_ring_write(ring, idx);
> +       amdgpu_ring_write(ring, 0);
> +       amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
> +                               xgpu->reg_val_offs * 4));
> +       amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
> +                               xgpu->reg_val_offs * 4));
> +}
> +
> +static void xgpu_kiq_ring_emit_wreg(struct amdgpu_ring *ring, u32 idx, u32 val)
> +{
> +       amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
> +       amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
> +       amdgpu_ring_write(ring, idx);
> +       amdgpu_ring_write(ring, 0);
> +       amdgpu_ring_write(ring, val);
> +}

These should be in gfx8.

Alex

> +
> +uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
> +{
> +       signed long r;
> +       uint32_t val;
> +       struct fence *f;
> +       struct amd_xgpu *xgpu = (struct amd_xgpu *)adev->priv_data;
> +       struct amdgpu_kiq *kiq = &adev->kiq;
> +
> +       if (in_interrupt())
> +               return 0;
> +
> +       mutex_lock(&xgpu->lock);
> +       amdgpu_ring_alloc(&kiq->ring, 32);
> +       amdgpu_ring_emit_hdp_flush(&kiq->ring);
> +       xgpu_kiq_ring_emit_rreg(&kiq->ring, reg);
> +       amdgpu_ring_emit_hdp_invalidate(&kiq->ring);
> +       amdgpu_fence_emit(&kiq->ring, &f);
> +       fence_get(f);
> +       amdgpu_ring_commit(&kiq->ring);
> +       mutex_unlock(&xgpu->lock);
> +
> +       r = fence_wait(f, false);
> +       fence_put(f);
> +       if (r)
> +               DRM_ERROR("wait for kiq fence error: %ld.\n", r);
> +       fence_put(f);
> +
> +       val = adev->wb.wb[xgpu->reg_val_offs];
> +
> +       return val;
> +}
> +
> +void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
> +{
> +       signed long r;
> +       struct fence *f;
> +       struct amd_xgpu *xgpu = (struct amd_xgpu *)adev->priv_data;
> +       struct amdgpu_kiq *kiq = &adev->kiq;
> +
> +       mutex_lock(&xgpu->lock);
> +       amdgpu_ring_alloc(&kiq->ring, 32);
> +       amdgpu_ring_emit_hdp_flush(&kiq->ring);
> +       xgpu_kiq_ring_emit_wreg(&kiq->ring, reg, v);
> +       amdgpu_ring_emit_hdp_invalidate(&kiq->ring);
> +       amdgpu_fence_emit(&kiq->ring, &f);
> +       fence_get(f);
> +       amdgpu_ring_commit(&kiq->ring);
> +       mutex_unlock(&xgpu->lock);
> +
> +       r = fence_wait(f, false);
> +       fence_put(f);
> +       if (r)
> +               DRM_ERROR("wait for kiq fence error: %ld.\n", r);
> +       fence_put(f);
> +}
> --
> 2.7.4
>
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