[PATCH 05/10] drm/amd/powerplay: enable DiDt feature for polaris10/11.
Bas Nieuwenhuizen
bas at basnieuwenhuizen.nl
Wed Jul 6 10:30:30 UTC 2016
On Wed, Jul 6, 2016 at 11:55 AM, Rex Zhu <Rex.Zhu at amd.com> wrote:
> DIDT is a power saving feature which helps limit power
> consumption in order to hit a target power allocation.
>
> Change-Id: Ibae481c2da6e393dc3e7756ebeb0a72dbe6e4e4d
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> 1.txt | 1294 ++++++++++++++++++++
Are you sure you want the 1.txt committed with this patch?
Also, I haven't got patch 6-10 of the 10 and neither has the
archive[1]. If you intended to send those too, you may want to resend.
Thanks,
Bas Nieuwenhuizen
[1] https://lists.freedesktop.org/archives/amd-gfx/2016-July/date.html
> .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 17 +-
> .../drm/amd/powerplay/hwmgr/polaris10_powertune.c | 531 ++++++++
> .../drm/amd/powerplay/hwmgr/polaris10_powertune.h | 11 +-
> 4 files changed, 1848 insertions(+), 5 deletions(-)
> create mode 100644 1.txt
>
> diff --git a/1.txt b/1.txt
> new file mode 100644
> index 0000000..9f32930
> --- /dev/null
> +++ b/1.txt
> @@ -0,0 +1,1294 @@
> +ERROR: Remove Gerrit Change-Id's before submitting upstream.
> +#9:
> +Change-Id: Ia26e4078124345508fe57ccf8e5812ff6c2c1230
> +
> +WARNING: line over 80 characters
> +#28: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c:2676:
> ++ "Failed to enable deep sleep master switch!", result = tmp_result);
> +
> +WARNING: line over 80 characters
> +#102: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:41:
> ++/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> +
> +WARNING: line over 80 characters
> +#103: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:42:
> ++ * Offset Mask Shift Value Type
> +
> +WARNING: line over 80 characters
> +#104: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:43:
> ++ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> +
> +WARNING: line over 80 characters
> +#106: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:45:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00060013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#107: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:46:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00860013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#108: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:47:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01060013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#109: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:48:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01860013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#110: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:49:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02060013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#111: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:50:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02860013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#112: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:51:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x03060013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#113: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:52:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x03860013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#114: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:53:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x04060013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#116: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:55:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x000E0013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#117: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:56:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x008E0013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#118: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:57:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x010E0013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#119: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:58:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x018E0013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#120: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:59:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x020E0013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#122: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:61:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00100013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#123: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:62:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00900013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#124: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:63:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01100013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#125: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:64:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01900013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#126: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:65:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02100013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#127: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:66:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02900013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#133: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:72:
> ++/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> +
> +WARNING: line over 80 characters
> +#134: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:73:
> ++ * Offset Mask Shift Value Type
> +
> +WARNING: line over 80 characters
> +#135: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:74:
> ++ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> +
> +WARNING: line over 80 characters
> +#137: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:76:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00060011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#138: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:77:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00860011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#139: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:78:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01060011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#140: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:79:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01860011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#141: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:80:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02060011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#142: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:81:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02860011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#143: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:82:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x03060011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#144: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:83:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x03860011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#145: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:84:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x04060011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#147: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:86:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x000E0011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#148: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:87:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x008E0011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#149: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:88:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x010E0011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#150: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:89:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x018E0011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#151: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:90:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x020E0011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#153: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:92:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00100011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#154: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:93:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00900011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#155: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:94:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01100011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#156: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:95:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01900011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#157: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:96:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02100011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#158: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:97:
> ++ { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02900011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> +WARNING: line over 80 characters
> +#164: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:103:
> ++/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> +
> +WARNING: line over 80 characters
> +#165: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:104:
> ++ * Offset Mask Shift Value Type
> +
> +WARNING: line over 80 characters
> +#166: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:105:
> ++ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> +
> +WARNING: line over 80 characters
> +#168: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:107:
> ++ { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT, 0x0073, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#169: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:108:
> ++ { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT, 0x00ab, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#170: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:109:
> ++ { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT, 0x0084, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#171: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:110:
> ++ { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT, 0x005a, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#173: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:112:
> ++ { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT, 0x0067, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#174: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:113:
> ++ { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT, 0x0084, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#175: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:114:
> ++ { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT, 0x0027, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#176: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:115:
> ++ { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT, 0x0046, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#178: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:117:
> ++ { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT, 0x00aa, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#179: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:118:
> ++ { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#180: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:119:
> ++ { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#181: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:120:
> ++ { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#183: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:122:
> ++ { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MIN_POWER_MASK, DIDT_SQ_CTRL1__MIN_POWER__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#184: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:123:
> ++ { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#186: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:125:
> ++ { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__UNUSED_0_MASK, DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#187: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:126:
> ++ { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#189: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:128:
> ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3853, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#190: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:129:
> ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_0_MASK, DIDT_SQ_CTRL2__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#191: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:130:
> ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x005a, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#192: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:131:
> ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_1_MASK, DIDT_SQ_CTRL2__UNUSED_1__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#193: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:132:
> ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#194: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:133:
> ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_2_MASK, DIDT_SQ_CTRL2__UNUSED_2__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#196: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:135:
> ++ { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#197: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:136:
> ++ { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#198: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:137:
> ++ { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#199: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:138:
> ++ { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x0ebb, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#200: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:139:
> ++ { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__UNUSED_0_MASK, DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#202: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:141:
> ++ { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#203: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:142:
> ++ { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3853, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#204: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:143:
> ++ { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3153, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#205: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:144:
> ++ { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK, DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#207: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:146:
> ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#208: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:147:
> ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK, DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#209: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:148:
> ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#210: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:149:
> ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#211: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:150:
> ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#212: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:151:
> ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#213: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:152:
> ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#214: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:153:
> ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__UNUSED_0_MASK, DIDT_SQ_CTRL0__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#216: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:155:
> ++ { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT0_MASK, DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT, 0x000a, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#217: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:156:
> ++ { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT1_MASK, DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT, 0x0010, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#218: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:157:
> ++ { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT2_MASK, DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT, 0x0017, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#219: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:158:
> ++ { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT3_MASK, DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT, 0x002f, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#221: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:160:
> ++ { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT4_MASK, DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT, 0x0046, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#222: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:161:
> ++ { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT5_MASK, DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT, 0x005d, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#223: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:162:
> ++ { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT6_MASK, DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#224: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:163:
> ++ { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT7_MASK, DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#226: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:165:
> ++ { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#227: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:166:
> ++ { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#229: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:168:
> ++ { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__UNUSED_0_MASK, DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#230: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:169:
> ++ { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0x00ff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#232: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:171:
> ++ { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#233: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:172:
> ++ { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_0_MASK, DIDT_TD_CTRL2__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#234: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:173:
> ++ { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x000f, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#235: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:174:
> ++ { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_1_MASK, DIDT_TD_CTRL2__UNUSED_1__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#236: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:175:
> ++ { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#237: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:176:
> ++ { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_2_MASK, DIDT_TD_CTRL2__UNUSED_2__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#239: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:178:
> ++ { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#240: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:179:
> ++ { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#241: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:180:
> ++ { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#242: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:181:
> ++ { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#243: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:182:
> ++ { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__UNUSED_0_MASK, DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#245: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:184:
> ++ { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#246: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:185:
> ++ { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#247: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:186:
> ++ { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#248: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:187:
> ++ { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__UNUSED_0_MASK, DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#250: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:189:
> ++ { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#251: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:190:
> ++ { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__USE_REF_CLOCK_MASK, DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#252: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:191:
> ++ { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#253: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:192:
> ++ { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#254: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:193:
> ++ { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#255: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:194:
> ++ { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0009, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#256: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:195:
> ++ { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0009, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#257: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:196:
> ++ { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__UNUSED_0_MASK, DIDT_TD_CTRL0__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#259: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:198:
> ++ { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT, 0x0004, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#260: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:199:
> ++ { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT, 0x0037, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#261: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:200:
> ++ { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#262: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:201:
> ++ { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT, 0x00ff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#264: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:203:
> ++ { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT, 0x0054, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#265: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:204:
> ++ { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#266: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:205:
> ++ { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#267: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:206:
> ++ { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#269: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:208:
> ++ { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MIN_POWER_MASK, DIDT_TCP_CTRL1__MIN_POWER__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#270: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:209:
> ++ { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MAX_POWER_MASK, DIDT_TCP_CTRL1__MAX_POWER__SHIFT, 0xffff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#272: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:211:
> ++ { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__UNUSED_0_MASK, DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#273: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:212:
> ++ { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#275: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:214:
> ++ { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#276: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:215:
> ++ { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_0_MASK, DIDT_TCP_CTRL2__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#277: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:216:
> ++ { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x0032, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#278: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:217:
> ++ { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_1_MASK, DIDT_TCP_CTRL2__UNUSED_1__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#279: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:218:
> ++ { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#280: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:219:
> ++ { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_2_MASK, DIDT_TCP_CTRL2__UNUSED_2__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#282: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:221:
> ++ { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#283: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:222:
> ++ { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#284: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:223:
> ++ { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#285: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:224:
> ++ { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#286: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:225:
> ++ { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__UNUSED_0_MASK, DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#288: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:227:
> ++ { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#289: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:228:
> ++ { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#290: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:229:
> ++ { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#291: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:230:
> ++ { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK, DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#293: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:232:
> ++ { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#294: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:233:
> ++ { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK, DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#295: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:234:
> ++ { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#296: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:235:
> ++ { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#297: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:236:
> ++ { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#298: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:237:
> ++ { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#299: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:238:
> ++ { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#300: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:239:
> ++ { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__UNUSED_0_MASK, DIDT_TCP_CTRL0__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#306: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:245:
> ++/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> +
> +WARNING: line over 80 characters
> +#307: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:246:
> ++ * Offset Mask Shift Value Type
> +
> +WARNING: line over 80 characters
> +#308: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:247:
> ++ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> +
> +WARNING: line over 80 characters
> +#310: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:249:
> ++ { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT, 0x0073, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#311: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:250:
> ++ { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT, 0x00ab, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#312: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:251:
> ++ { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT, 0x0084, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#313: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:252:
> ++ { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT, 0x005a, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#315: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:254:
> ++ { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT, 0x0067, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#316: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:255:
> ++ { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT, 0x0084, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#317: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:256:
> ++ { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT, 0x0027, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#318: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:257:
> ++ { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT, 0x0046, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#320: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:259:
> ++ { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT, 0x00aa, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#321: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:260:
> ++ { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#322: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:261:
> ++ { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#323: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:262:
> ++ { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#325: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:264:
> ++ { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MIN_POWER_MASK, DIDT_SQ_CTRL1__MIN_POWER__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#326: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:265:
> ++ { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#328: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:267:
> ++ { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__UNUSED_0_MASK, DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#329: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:268:
> ++ { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#331: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:270:
> ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3853, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#332: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:271:
> ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_0_MASK, DIDT_SQ_CTRL2__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#333: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:272:
> ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x005a, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#334: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:273:
> ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_1_MASK, DIDT_SQ_CTRL2__UNUSED_1__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#335: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:274:
> ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#336: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:275:
> ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_2_MASK, DIDT_SQ_CTRL2__UNUSED_2__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#338: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:277:
> ++ { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#339: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:278:
> ++ { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#340: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:279:
> ++ { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#341: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:280:
> ++ { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x0ebb, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#342: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:281:
> ++ { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__UNUSED_0_MASK, DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#344: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:283:
> ++ { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#345: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:284:
> ++ { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3853, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#346: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:285:
> ++ { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3153, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#347: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:286:
> ++ { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK, DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#349: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:288:
> ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#350: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:289:
> ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK, DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#351: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:290:
> ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#352: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:291:
> ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#353: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:292:
> ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#354: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:293:
> ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#355: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:294:
> ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#356: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:295:
> ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__UNUSED_0_MASK, DIDT_SQ_CTRL0__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#358: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:297:
> ++ { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT0_MASK, DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT, 0x000a, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#359: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:298:
> ++ { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT1_MASK, DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT, 0x0010, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#360: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:299:
> ++ { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT2_MASK, DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT, 0x0017, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#361: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:300:
> ++ { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT3_MASK, DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT, 0x002f, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#363: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:302:
> ++ { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT4_MASK, DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT, 0x0046, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#364: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:303:
> ++ { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT5_MASK, DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT, 0x005d, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#365: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:304:
> ++ { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT6_MASK, DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#366: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:305:
> ++ { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT7_MASK, DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#368: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:307:
> ++ { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#369: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:308:
> ++ { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#371: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:310:
> ++ { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__UNUSED_0_MASK, DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#372: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:311:
> ++ { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0x00ff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#374: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:313:
> ++ { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#375: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:314:
> ++ { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_0_MASK, DIDT_TD_CTRL2__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#376: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:315:
> ++ { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x000f, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#377: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:316:
> ++ { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_1_MASK, DIDT_TD_CTRL2__UNUSED_1__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#378: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:317:
> ++ { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#379: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:318:
> ++ { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_2_MASK, DIDT_TD_CTRL2__UNUSED_2__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#381: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:320:
> ++ { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#382: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:321:
> ++ { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#383: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:322:
> ++ { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#384: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:323:
> ++ { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#385: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:324:
> ++ { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__UNUSED_0_MASK, DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#387: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:326:
> ++ { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#388: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:327:
> ++ { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#389: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:328:
> ++ { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#390: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:329:
> ++ { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__UNUSED_0_MASK, DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#392: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:331:
> ++ { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#393: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:332:
> ++ { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__USE_REF_CLOCK_MASK, DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#394: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:333:
> ++ { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#395: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:334:
> ++ { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#396: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:335:
> ++ { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#397: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:336:
> ++ { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0008, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#398: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:337:
> ++ { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0008, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#399: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:338:
> ++ { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__UNUSED_0_MASK, DIDT_TD_CTRL0__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#401: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:340:
> ++ { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT, 0x0004, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#402: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:341:
> ++ { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT, 0x0037, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#403: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:342:
> ++ { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#404: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:343:
> ++ { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT, 0x00ff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#406: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:345:
> ++ { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT, 0x0054, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#407: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:346:
> ++ { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#408: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:347:
> ++ { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#409: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:348:
> ++ { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#411: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:350:
> ++ { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MIN_POWER_MASK, DIDT_TCP_CTRL1__MIN_POWER__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#412: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:351:
> ++ { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MAX_POWER_MASK, DIDT_TCP_CTRL1__MAX_POWER__SHIFT, 0xffff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#414: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:353:
> ++ { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__UNUSED_0_MASK, DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#415: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:354:
> ++ { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#417: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:356:
> ++ { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#418: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:357:
> ++ { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_0_MASK, DIDT_TCP_CTRL2__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#419: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:358:
> ++ { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x0032, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#420: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:359:
> ++ { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_1_MASK, DIDT_TCP_CTRL2__UNUSED_1__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#421: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:360:
> ++ { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#422: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:361:
> ++ { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_2_MASK, DIDT_TCP_CTRL2__UNUSED_2__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#424: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:363:
> ++ { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#425: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:364:
> ++ { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#426: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:365:
> ++ { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#427: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:366:
> ++ { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#428: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:367:
> ++ { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__UNUSED_0_MASK, DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#430: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:369:
> ++ { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#431: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:370:
> ++ { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#432: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:371:
> ++ { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#433: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:372:
> ++ { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK, DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#435: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:374:
> ++ { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#436: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:375:
> ++ { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK, DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#437: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:376:
> ++ { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#438: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:377:
> ++ { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#439: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:378:
> ++ { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#440: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:379:
> ++ { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#441: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:380:
> ++ { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#442: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:381:
> ++ { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__UNUSED_0_MASK, DIDT_TCP_CTRL0__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> +WARNING: line over 80 characters
> +#460: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:569:
> ++ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping)) {
> +
> +WARNING: line over 80 characters
> +#461: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:570:
> ++ data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0);
> +
> +WARNING: line over 80 characters
> +#463: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:572:
> ++ data |= ((en << DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK);
> +
> +WARNING: line over 80 characters
> +#464: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:573:
> ++ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0, data);
> +
> +WARNING: line over 80 characters
> +#469: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:578:
> ++ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping)) {
> +
> +WARNING: line over 80 characters
> +#470: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:579:
> ++ data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0);
> +
> +WARNING: line over 80 characters
> +#472: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:581:
> ++ data |= ((en << DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK);
> +
> +WARNING: line over 80 characters
> +#473: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:582:
> ++ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0, data);
> +
> +WARNING: line over 80 characters
> +#478: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:587:
> ++ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping)) {
> +
> +WARNING: line over 80 characters
> +#479: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:588:
> ++ data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0);
> +
> +WARNING: line over 80 characters
> +#481: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:590:
> ++ data |= ((en << DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK);
> +
> +WARNING: line over 80 characters
> +#482: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:591:
> ++ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0, data);
> +
> +WARNING: line over 80 characters
> +#487: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:596:
> ++ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) {
> +
> +WARNING: line over 80 characters
> +#488: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:597:
> ++ data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0);
> +
> +WARNING: line over 80 characters
> +#490: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:599:
> ++ data |= ((en << DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK);
> +
> +WARNING: line over 80 characters
> +#491: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:600:
> ++ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0, data);
> +
> +WARNING: line over 80 characters
> +#497: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:606:
> ++ result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_Didt_Block_Function, DIDTBlock_Info);
> +
> +WARNING: line over 80 characters
> +#509: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:618:
> ++ PP_ASSERT_WITH_CODE((config_regs != NULL), "Invalid config register table.", return -1);
> +
> +WARNING: line over 80 characters
> +#513: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:622:
> ++ cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
> +
> +WARNING: line over 80 characters
> +#517: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:626:
> ++ data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset);
> +
> +WARNING: line over 80 characters
> +#521: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:630:
> ++ data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset);
> +
> +WARNING: line over 80 characters
> +#525: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:634:
> ++ data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset);
> +
> +WARNING: line over 80 characters
> +#529: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:638:
> ++ data = cgs_read_register(hwmgr->device, config_regs->offset);
> +
> +WARNING: line over 80 characters
> +#534: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:643:
> ++ data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
> +
> +WARNING: line over 80 characters
> +#539: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:648:
> ++ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset, data);
> +
> +WARNING: line over 80 characters
> +#543: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:652:
> ++ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data);
> +
> +WARNING: line over 80 characters
> +#547: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:656:
> ++ cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data);
> +
> +WARNING: line over 80 characters
> +#551: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:660:
> ++ cgs_write_register(hwmgr->device, config_regs->offset, data);
> +
> +WARNING: line over 80 characters
> +#578: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:687:
> ++ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping) ||
> +
> +WARNING: line over 80 characters
> +#579: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:688:
> ++ phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping) ||
> +
> +WARNING: line over 80 characters
> +#580: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:689:
> ++ phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping) ||
> +
> +WARNING: line over 80 characters
> +#581: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:690:
> ++ phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) {
> +
> +WARNING: line over 80 characters
> +#587: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:696:
> ++ value = SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK
> +
> +WARNING: line over 80 characters
> +#588: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:697:
> ++ | SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK
> +
> +WARNING: line over 80 characters
> +#589: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:698:
> ++ | (count << SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT);
> +
> +WARNING: line over 80 characters
> +#590: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:699:
> ++ cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value);
> +
> +WARNING: line over 80 characters
> +#593: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:702:
> ++ result = polaris10_program_pt_config_registers(hwmgr, GCCACConfig_Polaris10);
> +
> +WARNING: line over 80 characters
> +#594: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:703:
> ++ PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
> +
> +WARNING: line over 80 characters
> +#595: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:704:
> ++ result = polaris10_program_pt_config_registers(hwmgr, DIDTConfig_Polaris10);
> +
> +WARNING: line over 80 characters
> +#596: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:705:
> ++ PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
> +
> +WARNING: line over 80 characters
> +#598: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:707:
> ++ result = polaris10_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
> +
> +WARNING: line over 80 characters
> +#599: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:708:
> ++ PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
> +
> +WARNING: line over 80 characters
> +#600: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:709:
> ++ result = polaris10_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11);
> +
> +WARNING: line over 80 characters
> +#601: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:710:
> ++ PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
> +
> +WARNING: line over 80 characters
> +#607: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:716:
> ++ PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", return result);
> +
> +WARNING: line over 80 characters
> +#619: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:728:
> ++ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping) ||
> +
> +WARNING: line over 80 characters
> +#620: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:729:
> ++ phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping) ||
> +
> +WARNING: line over 80 characters
> +#621: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:730:
> ++ phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping) ||
> +
> +WARNING: line over 80 characters
> +#622: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:731:
> ++ phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) {
> +
> +WARNING: line over 80 characters
> +#626: FILE: drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c:735:
> ++ PP_ASSERT_WITH_CODE((result == 0), "Post DIDT enable clock gating failed.", return result);
> +
> +total: 1 errors, 321 warnings, 631 lines checked
> +
> +0001-drm-amd-powerplay-enable-DiDt-feature-for-polaris10-.patch has style problems, please review.
> +
> +NOTE: If any of the errors are false positives, please report
> + them to the maintainer, see CHECKPATCH in MAINTAINERS.
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
> index 474f262..67c1cf0 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
> @@ -2671,6 +2671,10 @@ int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
> PP_ASSERT_WITH_CODE((0 == tmp_result),
> "Failed to enable deep sleep master switch!", result = tmp_result);
>
> + tmp_result = polaris10_enable_didt_config(hwmgr);
> + PP_ASSERT_WITH_CODE((tmp_result == 0),
> + "Failed to enable deep sleep master switch!", result = tmp_result);
> +
> tmp_result = polaris10_start_dpm(hwmgr);
> PP_ASSERT_WITH_CODE((0 == tmp_result),
> "Failed to start DPM!", result = tmp_result);
> @@ -2810,13 +2814,13 @@ int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
> PHM_PlatformCaps_DynamicUVDState);
>
> /* power tune caps Assume disabled */
> - phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
> + phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> PHM_PlatformCaps_SQRamping);
> - phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
> + phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> PHM_PlatformCaps_DBRamping);
> - phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
> + phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> PHM_PlatformCaps_TDRamping);
> - phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
> + phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> PHM_PlatformCaps_TCPRamping);
>
> if (hwmgr->powercontainment_enabled)
> @@ -3642,6 +3646,7 @@ static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
> hwmgr->platform_descriptor.platformCaps,
> PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
>
> +
> disable_mclk_switching = (1 < info.display_count) ||
> disable_mclk_switching_for_frame_lock;
>
> @@ -4618,6 +4623,8 @@ static int polaris10_notify_smc_display(struct pp_hwmgr *hwmgr)
> return (smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ? 0 : -EINVAL;
> }
>
> +
> +
> static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
> {
> int tmp_result, result = 0;
> @@ -4726,6 +4733,7 @@ int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwm
> if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
> polaris10_notify_smc_display_change(hwmgr, false);
>
> +
> return 0;
> }
>
> @@ -4775,6 +4783,7 @@ int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
>
> cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
>
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
> index 5620e26..b9cb240 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
> @@ -28,10 +28,360 @@
> #include "polaris10_smumgr.h"
> #include "smu74_discrete.h"
> #include "pp_debug.h"
> +#include "gca/gfx_8_0_d.h"
> +#include "gca/gfx_8_0_sh_mask.h"
> +#include "oss/oss_3_0_sh_mask.h"
>
> #define VOLTAGE_SCALE 4
> #define POWERTUNE_DEFAULT_SET_MAX 1
>
> +uint32_t DIDTBlock_Info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK;
> +
> +struct polaris10_pt_config_reg GCCACConfig_Polaris10[] = {
> +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> + * Offset Mask Shift Value Type
> + * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> + */
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00060013, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00860013, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01060013, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01860013, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02060013, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02860013, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x03060013, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x03860013, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x04060013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x000E0013, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x008E0013, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x010E0013, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x018E0013, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x020E0013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00100013, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00900013, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01100013, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01900013, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02100013, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02900013, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> + { 0xFFFFFFFF }
> +};
> +
> +struct polaris10_pt_config_reg GCCACConfig_Polaris11[] = {
> +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> + * Offset Mask Shift Value Type
> + * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> + */
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00060011, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00860011, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01060011, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01860011, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02060011, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02860011, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x03060011, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x03860011, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x04060011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x000E0011, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x008E0011, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x010E0011, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x018E0011, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x020E0011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00100011, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00900011, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01100011, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01900011, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02100011, POLARIS10_CONFIGREG_GC_CAC_IND },
> + { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02900011, POLARIS10_CONFIGREG_GC_CAC_IND },
> +
> + { 0xFFFFFFFF }
> +};
> +
> +struct polaris10_pt_config_reg DIDTConfig_Polaris10[] = {
> +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> + * Offset Mask Shift Value Type
> + * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> + */
> + { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT, 0x0073, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT, 0x00ab, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT, 0x0084, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT, 0x005a, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT, 0x0067, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT, 0x0084, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT, 0x0027, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT, 0x0046, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT, 0x00aa, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MIN_POWER_MASK, DIDT_SQ_CTRL1__MIN_POWER__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__UNUSED_0_MASK, DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3853, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_0_MASK, DIDT_SQ_CTRL2__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x005a, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_1_MASK, DIDT_SQ_CTRL2__UNUSED_1__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_2_MASK, DIDT_SQ_CTRL2__UNUSED_2__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x0ebb, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__UNUSED_0_MASK, DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3853, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3153, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK, DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK, DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__UNUSED_0_MASK, DIDT_SQ_CTRL0__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT0_MASK, DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT, 0x000a, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT1_MASK, DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT, 0x0010, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT2_MASK, DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT, 0x0017, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT3_MASK, DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT, 0x002f, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT4_MASK, DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT, 0x0046, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT5_MASK, DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT, 0x005d, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT6_MASK, DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT7_MASK, DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__UNUSED_0_MASK, DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0x00ff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_0_MASK, DIDT_TD_CTRL2__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x000f, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_1_MASK, DIDT_TD_CTRL2__UNUSED_1__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_2_MASK, DIDT_TD_CTRL2__UNUSED_2__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__UNUSED_0_MASK, DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__UNUSED_0_MASK, DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__USE_REF_CLOCK_MASK, DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0009, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0009, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__UNUSED_0_MASK, DIDT_TD_CTRL0__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT, 0x0004, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT, 0x0037, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT, 0x00ff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT, 0x0054, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MIN_POWER_MASK, DIDT_TCP_CTRL1__MIN_POWER__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MAX_POWER_MASK, DIDT_TCP_CTRL1__MAX_POWER__SHIFT, 0xffff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__UNUSED_0_MASK, DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_0_MASK, DIDT_TCP_CTRL2__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x0032, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_1_MASK, DIDT_TCP_CTRL2__UNUSED_1__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_2_MASK, DIDT_TCP_CTRL2__UNUSED_2__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__UNUSED_0_MASK, DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK, DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK, DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__UNUSED_0_MASK, DIDT_TCP_CTRL0__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { 0xFFFFFFFF }
> +};
> +
> +struct polaris10_pt_config_reg DIDTConfig_Polaris11[] = {
> +/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> + * Offset Mask Shift Value Type
> + * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> + */
> + { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT, 0x0073, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT, 0x00ab, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT, 0x0084, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT, 0x005a, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT, 0x0067, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT, 0x0084, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT, 0x0027, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT, 0x0046, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT, 0x00aa, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MIN_POWER_MASK, DIDT_SQ_CTRL1__MIN_POWER__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__UNUSED_0_MASK, DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3853, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_0_MASK, DIDT_SQ_CTRL2__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x005a, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_1_MASK, DIDT_SQ_CTRL2__UNUSED_1__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_2_MASK, DIDT_SQ_CTRL2__UNUSED_2__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x0ebb, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__UNUSED_0_MASK, DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3853, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3153, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK, DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK, DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__UNUSED_0_MASK, DIDT_SQ_CTRL0__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT0_MASK, DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT, 0x000a, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT1_MASK, DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT, 0x0010, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT2_MASK, DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT, 0x0017, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT3_MASK, DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT, 0x002f, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT4_MASK, DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT, 0x0046, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT5_MASK, DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT, 0x005d, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT6_MASK, DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT7_MASK, DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__UNUSED_0_MASK, DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0x00ff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_0_MASK, DIDT_TD_CTRL2__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x000f, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_1_MASK, DIDT_TD_CTRL2__UNUSED_1__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_2_MASK, DIDT_TD_CTRL2__UNUSED_2__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__UNUSED_0_MASK, DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__UNUSED_0_MASK, DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__USE_REF_CLOCK_MASK, DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0008, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0008, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__UNUSED_0_MASK, DIDT_TD_CTRL0__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT, 0x0004, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT, 0x0037, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT, 0x00ff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT, 0x0054, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MIN_POWER_MASK, DIDT_TCP_CTRL1__MIN_POWER__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MAX_POWER_MASK, DIDT_TCP_CTRL1__MAX_POWER__SHIFT, 0xffff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__UNUSED_0_MASK, DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_0_MASK, DIDT_TCP_CTRL2__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x0032, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_1_MASK, DIDT_TCP_CTRL2__UNUSED_1__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_2_MASK, DIDT_TCP_CTRL2__UNUSED_2__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__UNUSED_0_MASK, DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK, DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> +
> + { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK, DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, POLARIS10_CONFIGREG_DIDT_IND },
> + { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__UNUSED_0_MASK, DIDT_TCP_CTRL0__UNUSED_0__SHIFT, 0x0000, POLARIS10_CONFIGREG_DIDT_IND },
> + { 0xFFFFFFFF }
> +};
> +
> static const struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
> /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
> * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
> @@ -209,6 +559,187 @@ static int polaris10_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> +static int polaris10_enable_didt(struct pp_hwmgr *hwmgr, const bool enable)
> +{
> +
> + uint32_t en = enable ? 1 : 0;
> + int32_t result = 0;
> + uint32_t data;
> +
> + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping)) {
> + data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0);
> + data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
> + data |= ((en << DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK);
> + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0, data);
> + DIDTBlock_Info &= ~SQ_Enable_MASK;
> + DIDTBlock_Info |= en << SQ_Enable_SHIFT;
> + }
> +
> + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping)) {
> + data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0);
> + data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
> + data |= ((en << DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK);
> + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0, data);
> + DIDTBlock_Info &= ~DB_Enable_MASK;
> + DIDTBlock_Info |= en << DB_Enable_SHIFT;
> + }
> +
> + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping)) {
> + data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0);
> + data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
> + data |= ((en << DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK);
> + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0, data);
> + DIDTBlock_Info &= ~TD_Enable_MASK;
> + DIDTBlock_Info |= en << TD_Enable_SHIFT;
> + }
> +
> + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) {
> + data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0);
> + data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
> + data |= ((en << DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK);
> + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0, data);
> + DIDTBlock_Info &= ~TCP_Enable_MASK;
> + DIDTBlock_Info |= en << TCP_Enable_SHIFT;
> + }
> +
> + if (enable)
> + result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_Didt_Block_Function, DIDTBlock_Info);
> +
> + return result;
> +}
> +
> +static int polaris10_program_pt_config_registers(struct pp_hwmgr *hwmgr,
> + struct polaris10_pt_config_reg *cac_config_regs)
> +{
> + struct polaris10_pt_config_reg *config_regs = cac_config_regs;
> + uint32_t cache = 0;
> + uint32_t data = 0;
> +
> + PP_ASSERT_WITH_CODE((config_regs != NULL), "Invalid config register table.", return -EINVAL);
> +
> + while (config_regs->offset != 0xFFFFFFFF) {
> + if (config_regs->type == POLARIS10_CONFIGREG_CACHE)
> + cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
> + else {
> + switch (config_regs->type) {
> + case POLARIS10_CONFIGREG_SMC_IND:
> + data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset);
> + break;
> +
> + case POLARIS10_CONFIGREG_DIDT_IND:
> + data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset);
> + break;
> +
> + case POLARIS10_CONFIGREG_GC_CAC_IND:
> + data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset);
> + break;
> +
> + default:
> + data = cgs_read_register(hwmgr->device, config_regs->offset);
> + break;
> + }
> +
> + data &= ~config_regs->mask;
> + data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
> + data |= cache;
> +
> + switch (config_regs->type) {
> + case POLARIS10_CONFIGREG_SMC_IND:
> + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset, data);
> + break;
> +
> + case POLARIS10_CONFIGREG_DIDT_IND:
> + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data);
> + break;
> +
> + case POLARIS10_CONFIGREG_GC_CAC_IND:
> + cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data);
> + break;
> +
> + default:
> + cgs_write_register(hwmgr->device, config_regs->offset, data);
> + break;
> + }
> + cache = 0;
> + }
> +
> + config_regs++;
> + }
> +
> + return 0;
> +}
> +
> +int polaris10_enable_didt_config(struct pp_hwmgr *hwmgr)
> +{
> + int result;
> + uint32_t num_se = 0;
> + uint32_t count, value, value2;
> + struct cgs_system_info sys_info = {0};
> +
> + sys_info.size = sizeof(struct cgs_system_info);
> + sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
> + result = cgs_query_system_info(hwmgr->device, &sys_info);
> +
> +
> + if (result == 0)
> + num_se = sys_info.value;
> +
> + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping) ||
> + phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping) ||
> + phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping) ||
> + phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) {
> +
> + /* TO DO Pre DIDT disable clock gating */
> + value = 0;
> + value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX);
> + for (count = 0; count < num_se; count++) {
> + value = SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK
> + | SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK
> + | (count << SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT);
> + cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value);
> +
> + if (hwmgr->chip_id == CHIP_POLARIS10) {
> + result = polaris10_program_pt_config_registers(hwmgr, GCCACConfig_Polaris10);
> + PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
> + result = polaris10_program_pt_config_registers(hwmgr, DIDTConfig_Polaris10);
> + PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
> + } else if (hwmgr->chip_id == CHIP_POLARIS11) {
> + result = polaris10_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
> + PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
> + result = polaris10_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11);
> + PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
> + }
> + }
> + cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value2);
> +
> + result = polaris10_enable_didt(hwmgr, true);
> + PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", return result);
> +
> + /* TO DO Post DIDT enable clock gating */
> + }
> +
> + return 0;
> +}
> +
> +int polaris10_disable_didt_config(struct pp_hwmgr *hwmgr)
> +{
> + int result;
> +
> + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping) ||
> + phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping) ||
> + phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping) ||
> + phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) {
> + /* TO DO Pre DIDT disable clock gating */
> +
> + result = polaris10_enable_didt(hwmgr, false);
> + PP_ASSERT_WITH_CODE((result == 0), "Post DIDT enable clock gating failed.", return result);
> + /* TO DO Post DIDT enable clock gating */
> + }
> +
> + return 0;
> +}
> +
> +
> static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
> {
> struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h
> index d492d6d..bc78e28 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h
> @@ -27,6 +27,7 @@ enum polaris10_pt_config_reg_type {
> POLARIS10_CONFIGREG_MMR = 0,
> POLARIS10_CONFIGREG_SMC_IND,
> POLARIS10_CONFIGREG_DIDT_IND,
> + POLARIS10_CONFIGREG_GC_CAC_IND,
> POLARIS10_CONFIGREG_CACHE,
> POLARIS10_CONFIGREG_MAX
> };
> @@ -49,6 +50,14 @@ enum polaris10_pt_config_reg_type {
> #define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002
> #define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004
>
> +#define ixGC_CAC_CNTL 0x0000
> +#define ixDIDT_SQ_STALL_CTRL 0x0004
> +#define ixDIDT_SQ_TUNING_CTRL 0x0005
> +#define ixDIDT_TD_STALL_CTRL 0x0044
> +#define ixDIDT_TD_TUNING_CTRL 0x0045
> +#define ixDIDT_TCP_STALL_CTRL 0x0064
> +#define ixDIDT_TCP_TUNING_CTRL 0x0065
> +
> struct polaris10_pt_config_reg {
> uint32_t offset;
> uint32_t mask;
> @@ -80,6 +89,6 @@ int polaris10_enable_power_containment(struct pp_hwmgr *hwmgr);
> int polaris10_disable_power_containment(struct pp_hwmgr *hwmgr);
> int polaris10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
> int polaris10_power_control_set_level(struct pp_hwmgr *hwmgr);
> -
> +int polaris10_enable_didt_config(struct pp_hwmgr *hwmgr);
> #endif /* POLARIS10_POWERTUNE_H */
>
> --
> 1.9.1
>
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