[PATCH 04/10] drm/amdgpu: add read/write function for GC CAC programming
Alex Deucher
alexdeucher at gmail.com
Wed Jul 6 20:49:42 UTC 2016
On Wed, Jul 6, 2016 at 5:55 AM, Rex Zhu <Rex.Zhu at amd.com> wrote:
> Create a GC_CAC_IND_INDEX/DATA pair of funcitons to program
> all the CAC registers
>
> Change-Id: I4d2b8d2225a6f9d0a2fea63bcaf7e8acb27af330
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 ++++++
> drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 4 ++++
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++
> drivers/gpu/drm/amd/amdgpu/vi.c | 25 +++++++++++++++++++++++++
> drivers/gpu/drm/amd/include/cgs_common.h | 1 +
> 5 files changed, 40 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index e96ac17..747d845 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -2023,6 +2023,10 @@ struct amdgpu_device {
> spinlock_t didt_idx_lock;
> amdgpu_rreg_t didt_rreg;
> amdgpu_wreg_t didt_wreg;
> + /* protects concurrent gc_cac register access */
> + spinlock_t gc_cac_idx_lock;
> + amdgpu_rreg_t gc_cac_rreg;
> + amdgpu_wreg_t gc_cac_wreg;
> /* protects concurrent ENDPOINT (audio) register access */
> spinlock_t audio_endpt_idx_lock;
> amdgpu_block_rreg_t audio_endpt_rreg;
> @@ -2156,6 +2160,8 @@ bool amdgpu_device_has_dal_support(struct amdgpu_device *adev);
> #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
> #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
> #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
> +#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
> +#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
> #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
> #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
> #define WREG32_P(reg, val, mask) \
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> index f413050..5556ce9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> @@ -312,6 +312,8 @@ static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
> return RREG32_UVD_CTX(index);
> case CGS_IND_REG__DIDT:
> return RREG32_DIDT(index);
> + case CGS_IND_REG_GC_CAC:
> + return RREG32_GC_CAC(index);
> case CGS_IND_REG__AUDIO_ENDPT:
> DRM_ERROR("audio endpt register access not implemented.\n");
> return 0;
> @@ -336,6 +338,8 @@ static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
> return WREG32_UVD_CTX(index, value);
> case CGS_IND_REG__DIDT:
> return WREG32_DIDT(index, value);
> + case CGS_IND_REG_GC_CAC:
> + return WREG32_GC_CAC(index, value);
> case CGS_IND_REG__AUDIO_ENDPT:
> DRM_ERROR("audio endpt register access not implemented.\n");
> return;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 99764f9..1da280e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1526,9 +1526,12 @@ int amdgpu_device_init(struct amdgpu_device *adev,
> adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
> adev->didt_rreg = &amdgpu_invalid_rreg;
> adev->didt_wreg = &amdgpu_invalid_wreg;
> + adev->gc_cac_rreg = &amdgpu_invalid_rreg;
> + adev->gc_cac_wreg = &amdgpu_invalid_wreg;
> adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
> adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
>
> +
> DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
> amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
> pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
> @@ -1553,6 +1556,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
> spin_lock_init(&adev->pcie_idx_lock);
> spin_lock_init(&adev->uvd_ctx_idx_lock);
> spin_lock_init(&adev->didt_idx_lock);
> + spin_lock_init(&adev->gc_cac_idx_lock);
> spin_lock_init(&adev->audio_endpt_idx_lock);
>
> adev->rmmio_base = pci_resource_start(adev->pdev, 5);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 4105395..91d71e3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -204,6 +204,29 @@ static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
> spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
> }
>
> +static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
> +{
> + unsigned long flags;
> + u32 r;
> +
> + spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
> + WREG32(mmGC_CAC_IND_INDEX, (reg));
> + r = RREG32(mmGC_CAC_IND_DATA);
> + spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
> + return r;
> +}
> +
> +static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
> +{
> + unsigned long flags;
> +
> + spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
> + WREG32(mmGC_CAC_IND_INDEX, (reg));
> + WREG32(mmGC_CAC_IND_DATA, (v));
> + spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
> +}
> +
> +
> static const u32 tonga_mgcg_cgcg_init[] =
> {
> mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
> @@ -1487,6 +1510,8 @@ static int vi_common_early_init(void *handle)
> adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
> adev->didt_rreg = &vi_didt_rreg;
> adev->didt_wreg = &vi_didt_wreg;
> + adev->gc_cac_rreg = &vi_gc_cac_rreg;
> + adev->gc_cac_wreg = &vi_gc_cac_wreg;
>
> adev->asic_funcs = &vi_asic_funcs;
>
> diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
> index 4ea7f3d..0c8c85d 100644
> --- a/drivers/gpu/drm/amd/include/cgs_common.h
> +++ b/drivers/gpu/drm/amd/include/cgs_common.h
> @@ -49,6 +49,7 @@ enum cgs_ind_reg {
> CGS_IND_REG__SMC,
> CGS_IND_REG__UVD_CTX,
> CGS_IND_REG__DIDT,
> + CGS_IND_REG_GC_CAC,
> CGS_IND_REG__AUDIO_ENDPT
> };
>
> --
> 1.9.1
>
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