[PATCH] drm/amdgpu/gfx8: Double CP table size for ST/CZ

[zhoucm1]

On 2016年07月12日 05:22, Tom St Denis wrote:
> Was seeing GPU/CPU hangs with previous CP table size.
> With it doubled I've had a full day of uptime while
> running a variety of activities with PG/CG enabled.
What is the root cause? Does the CP table size need 4K alignment?
We need to identify it before pushing.

Regards,
David Zhou
>
> Signed-off-by: Tom St Denis <tom.stdenis at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 24faddbd9a5d..cbbbd5f1da0f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -1293,7 +1293,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
>   
>   	if ((adev->asic_type == CHIP_CARRIZO) ||
>   	    (adev->asic_type == CHIP_STONEY)) {
> -		adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
> +		adev->gfx.rlc.cp_table_size = (ALIGN(96 * 5 * 4, 2048) + (64 * 1024)) * 2; /* JT + GDS */
>   		if (adev->gfx.rlc.cp_table_obj == NULL) {
>   			r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
>   					     AMDGPU_GEM_DOMAIN_VRAM,