powerplay UVD CG (defaults to on)

[StDenis, Tom]

Hi Alex,


Thing is once the core is in use (and all times after that) UVD clocks are being gated (by firmware) as you'd expect.  For instance, UDEC_SCLK is reading ~10% by the debug tool while playing a 1080p h264 video on my CZ.  If I stop playing video the clock doesn't go back to 100% so FW is still gating it (reads 0%).


It's likely a late_init issue I just wanted to know if there was a technical reason to not have it gated after loading the module (like for PG it must be enabled after the core is initialized properly for instance which is why it's not supported in PP just yet).


Cheers,

Tom


________________________________
From: Deucher, Alexander
Sent: Thursday, July 14, 2016 13:59
To: StDenis, Tom; amd-gfx list
Subject: RE: powerplay UVD CG (defaults to on)


On asic powerup, the UVD clocks are not gated IIRC.  All the blocks that support clockgating get gated in amdgpu_late_init() in amdgpu_device which calls the set_clockgating_state() callback for each IP.  So they should be gated at that point.  You'll probably want to check and see what powerplay does in it's set_clockgating_state or late_init IP callbacks.  UVD and VCE are a bit trickier since they only support manual clock and powergating.



Alex



From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf Of StDenis, Tom
Sent: Thursday, July 14, 2016 10:05 AM
To: amd-gfx list
Subject: powerplay UVD CG (defaults to on)



Upon loading the module the UVD clocks are full on until you use the UVD block in which case CG kicks in.  This is on a boot with pg_mask=0 but cg_mask left alone (I'm trying to see if I can get a system hang with PG alone turned off).



That's probably a bug in powerplay though right?  I'd think on boot the UVD clocks should gate.  Is that on purpose or as a workaround for something?



Tom
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