[PATCH 3/3] drm/amdgpu: fix issue that when uvd dpm disabled, uvd clock remain high on polaris10 and fiji.

[Christian König]

Am 18.07.2016 um 18:59 schrieb Rex Zhu:
> also revert the workaround patch.
>
> Change-Id: I4523bf3abd74c449d2db3616e3508c55a2790ddc
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>

Might be a good idea to mention the original commit (upstream id) which 
introduced the workaround when reverting it.

Either way patch itself is Reviewed-by: Christian König 
<christian.koenig at amd.com>.

Regards,
Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c                          | 4 ----
>   drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c      | 2 +-
>   drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c | 2 +-
>   3 files changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> index d9c88d13..e19520c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> @@ -1106,10 +1106,6 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
>   	if (fences == 0 && handles == 0) {
>   		if (adev->pm.dpm_enabled) {
>   			amdgpu_dpm_enable_uvd(adev, false);
> -			/* just work around for uvd clock remain high even
> -			 * when uvd dpm disabled on Polaris10 */
> -			if (adev->asic_type == CHIP_POLARIS10)
> -				amdgpu_asic_set_uvd_clocks(adev, 0, 0);
>   		} else {
>   			amdgpu_asic_set_uvd_clocks(adev, 0, 0);
>   		}
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
> index e1b649b..5afe820 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
> @@ -56,7 +56,7 @@ int fiji_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
>   		fiji_update_uvd_dpm(hwmgr, false);
>   		cgs_set_clockgating_state(hwmgr->device,
>   					  AMD_IP_BLOCK_TYPE_UVD,
> -					  AMD_PG_STATE_UNGATE);
> +					  AMD_CG_STATE_UNGATE);
>   	}
>   
>   	return 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
> index 3d324d8..b5edb51 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
> @@ -116,7 +116,7 @@ int polaris10_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
>   		polaris10_update_uvd_dpm(hwmgr, false);
>   		cgs_set_clockgating_state(hwmgr->device,
>   				AMD_IP_BLOCK_TYPE_UVD,
> -				AMD_PG_STATE_UNGATE);
> +				AMD_CG_STATE_UNGATE);
>   	}
>   
>   	return 0;