[PATCH 1/3] drm/amdgpu: add bypass mode for vce3.0

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Monday, July 18, 2016 1:00 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 1/3] drm/amdgpu: add bypass mode for vce3.0
> 
> Change-Id: I68aa5431146b21990a998a777e00139f0478407f
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 30e8099..962aa5e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -604,6 +604,18 @@ static int vce_v3_0_process_interrupt(struct
> amdgpu_device *adev,
>  	return 0;
>  }
> 
> +static void vce_v3_set_bypass_mode(struct amdgpu_device *adev, bool
> enable)

For consistency, please change the function name to:
vce_v3_0_set_bypass_mode()

With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> +{
> +	u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
> +
> +	if (enable)
> +		tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
> +	else
> +		tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
> +
> +	WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
> +}
> +
>  static int vce_v3_0_set_clockgating_state(void *handle,
>  					  enum amd_clockgating_state state)
>  {
> @@ -611,6 +623,9 @@ static int vce_v3_0_set_clockgating_state(void
> *handle,
>  	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
>  	int i;
> 
> +	if (adev->asic_type == CHIP_POLARIS10)
> +		vce_v3_set_bypass_mode(adev, enable);
> +
>  	if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
>  		return 0;
> 
> --
> 1.9.1
> 
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