[PATCH v2] drm/amdgpu: change pcie_gen_cap magic code to macro

Deucher, Alexander Alexander.Deucher at amd.com
Wed Jun 22 12:50:52 UTC 2016


> -----Original Message-----
> From: Huang Rui [mailto:ray.huang at amd.com]
> Sent: Wednesday, June 22, 2016 1:50 AM
> To: amd-gfx at lists.freedesktop.org
> Cc: Deucher, Alexander; Huang, Ray; Huang, JinHuiEric; Wang, Qingqing
> Subject: [PATCH v2] drm/amdgpu: change pcie_gen_cap magic code to
> macro
> 
> This patch changes pcie_gen_cap magic code to macro to make it more
> readable.
> 
> Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> Reviewed-by: Rex Zhu <Rex.Zhu at amd.com>
> Signed-off-by: Huang Rui <ray.huang at amd.com>
> Cc: Eric Huang <JinHuiEric.Huang at amd.com>
> Cc: Ken Wang <Qingqing.Wang at amd.com>
> ---
> 
> Changes from V1 -> V2:
> - Move definitions to amd_pcie.h, because it would be better to reuse

V2 is:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> 
> Thanks
> Rui
> 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c            |  3 ---
>  drivers/gpu/drm/amd/include/amd_pcie.h                | 14 ++++++++++++++
>  drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c      |  4 ++--
>  drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c |  4 ++--
>  drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c     |  4 ++--
>  5 files changed, 20 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 7c0ca74..727a339 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1962,9 +1962,6 @@ retry:
>  	return r;
>  }
> 
> -#define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007  /* gen: chipset 1/2,
> asic 1/2/3 */
> -#define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16
> lanes */
> -
>  void amdgpu_get_pcie_info(struct amdgpu_device *adev)
>  {
>  	u32 mask;
> diff --git a/drivers/gpu/drm/amd/include/amd_pcie.h
> b/drivers/gpu/drm/amd/include/amd_pcie.h
> index 7c2a916..5eb895f 100644
> --- a/drivers/gpu/drm/amd/include/amd_pcie.h
> +++ b/drivers/gpu/drm/amd/include/amd_pcie.h
> @@ -37,6 +37,13 @@
>  #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK   0x0000FFFF
>  #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT  0
> 
> +/* gen: chipset 1/2, asic 1/2/3 */
> +#define AMDGPU_DEFAULT_PCIE_GEN_MASK
> (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 \
> +				      |
> CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 \
> +				      |
> CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 \
> +				      |
> CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 \
> +				      |
> CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3)
> +
>  /* Following flags shows PCIe lane width switch supported in driver which
> are decided by chipset and ASIC */
>  #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1          0x00010000
>  #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2          0x00020000
> @@ -47,4 +54,11 @@
>  #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32         0x00400000
>  #define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT       16
> 
> +/* 1/2/4/8/16 lanes */
> +#define AMDGPU_DEFAULT_PCIE_MLW_MASK
> (CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 \
> +				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \
> +				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \
> +				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \
> +				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
> +
>  #endif
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
> index 27cdcb0..0aee891 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
> @@ -731,7 +731,7 @@ static int fiji_hwmgr_backend_init(struct pp_hwmgr
> *hwmgr)
>  		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
>  		result = cgs_query_system_info(hwmgr->device, &sys_info);
>  		if (result)
> -			data->pcie_gen_cap = 0x30007;
> +			data->pcie_gen_cap =
> AMDGPU_DEFAULT_PCIE_GEN_MASK;
>  		else
>  			data->pcie_gen_cap = (uint32_t)sys_info.value;
>  		if (data->pcie_gen_cap &
> CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
> @@ -740,7 +740,7 @@ static int fiji_hwmgr_backend_init(struct pp_hwmgr
> *hwmgr)
>  		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
>  		result = cgs_query_system_info(hwmgr->device, &sys_info);
>  		if (result)
> -			data->pcie_lane_cap = 0x2f0000;
> +			data->pcie_lane_cap =
> AMDGPU_DEFAULT_PCIE_MLW_MASK;
>  		else
>  			data->pcie_lane_cap = (uint32_t)sys_info.value;
>  	} else {
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
> index 49c1e88..92292da 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
> @@ -3267,7 +3267,7 @@ int polaris10_hwmgr_backend_init(struct
> pp_hwmgr *hwmgr)
>  		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
>  		result = cgs_query_system_info(hwmgr->device, &sys_info);
>  		if (result)
> -			data->pcie_gen_cap = 0x30007;
> +			data->pcie_gen_cap =
> AMDGPU_DEFAULT_PCIE_GEN_MASK;
>  		else
>  			data->pcie_gen_cap = (uint32_t)sys_info.value;
>  		if (data->pcie_gen_cap &
> CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
> @@ -3276,7 +3276,7 @@ int polaris10_hwmgr_backend_init(struct
> pp_hwmgr *hwmgr)
>  		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
>  		result = cgs_query_system_info(hwmgr->device, &sys_info);
>  		if (result)
> -			data->pcie_lane_cap = 0x2f0000;
> +			data->pcie_lane_cap =
> AMDGPU_DEFAULT_PCIE_MLW_MASK;
>  		else
>  			data->pcie_lane_cap = (uint32_t)sys_info.value;
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
> index 33a6fa7..7840211 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
> @@ -4637,7 +4637,7 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr
> *hwmgr)
>  		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
>  		result = cgs_query_system_info(hwmgr->device, &sys_info);
>  		if (result)
> -			data->pcie_gen_cap = 0x30007;
> +			data->pcie_gen_cap =
> AMDGPU_DEFAULT_PCIE_GEN_MASK;
>  		else
>  			data->pcie_gen_cap = (uint32_t)sys_info.value;
>  		if (data->pcie_gen_cap &
> CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
> @@ -4646,7 +4646,7 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr
> *hwmgr)
>  		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
>  		result = cgs_query_system_info(hwmgr->device, &sys_info);
>  		if (result)
> -			data->pcie_lane_cap = 0x2f0000;
> +			data->pcie_lane_cap =
> AMDGPU_DEFAULT_PCIE_MLW_MASK;
>  		else
>  			data->pcie_lane_cap = (uint32_t)sys_info.value;
>  	} else {
> --
> 2.7.4



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