SDMA out-of-bounds write access of tiled surface

[Mads]

On 2016-06-22 16:46, Alex Deucher wrote:

> That's interesting. Note that all micro (1D) and macro tile parameters
> are the same on all Carrizos regardless of the memory configuration.
> That's determined by the tile mode arrays. Internal docs don't list
> any other tile mode configurations for Carrizo.
> The row size affects the value programmed in the GB_ADDR_CONFIG and
> related registers.
> 
> Alex

Just throwing this out there, but the Carrizo with the issues is running 
a custom modeline with resolution 1366x768. Don't know if this is of any 
significance at all, but thought you should know at least.

Can provide the modeline if necessary.

- Mads